公开(公告)号：US20160379847A1

公开(公告)日：2016-12-29

申请号：US15261354

申请日：2016-09-09

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Edward Fuergut

IPC: H01L21/56

CPC classification number: H01L21/566 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3121 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each including a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips.

Abstract translation: 公开了一种制造半导体芯片的方法。 在一个实施例中，该方法包括提供载体，提供多个半导体芯片，所述半导体芯片各自包括第一主面和与第一主面相对的第二主面以及连接第一和第二主面的侧面， 载体上的半导体芯片，其中第二主面面向载体，并且向半导体芯片的侧面施加封装材料。

公开(公告)号：US09496228B2

公开(公告)日：2016-11-15

申请号：US14987820

申请日：2016-01-05

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Joachim Mahler ,  Ivan Nikitin

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/4832 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments, an integrated circuit is provided. The integrated circuit may include a semiconductor chip and an electrically conductive composite material fixed to the semiconductor chip, wherein the electrically conductive composite material may include a metal, and wherein a coefficient of thermal expansion (CTE) value of the electrically conductive composite material may be lower than the CTE value of the metal.

Abstract translation: 在各种实施例中，提供集成电路。 集成电路可以包括固定到半导体芯片的半导体芯片和导电复合材料，其中导电复合材料可以包括金属，并且其中导电复合材料的热膨胀系数（CTE）值可以是 低于金属的CTE值。

公开(公告)号：US09455160B2

公开(公告)日：2016-09-27

申请号：US13741113

申请日：2013-01-14

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Edward Fuergut

IPC: H01L23/34 ,  H01L21/56 ,  H01L23/28 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/566 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3121 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00

Abstract: The method comprises providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each comprising a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips.

Abstract translation: 该方法包括提供载体，提供多个半导体芯片，所述半导体芯片各自包括第一主面和与第一主面相对的第二主面以及连接第一和第二主面的侧面，将半导体芯片放置在 载体，其中第二主面面向载体，并且将包封材料施加到半导体芯片的侧面。

公开(公告)号：US20150332938A1

公开(公告)日：2015-11-19

申请号：US14279752

申请日：2014-05-16

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Edward Fuergut ,  Irmgard Escher-Poeppel

IPC: H01L21/56 ,  H01L25/065 ,  H01L21/78

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68318 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A method of manufacturing an electronic device package includes structuring a metal layer to generate a structured metal layer having a plurality of openings. Semiconductor chips are placed into at least some of the openings. An encapsulating material is applied over the structured metal layer and the semiconductor chips to form an encapsulation body. The encapsulation body is separated into a plurality of electronic device packages.

Abstract translation: 制造电子器件封装的方法包括构造金属层以产生具有多个开口的结构化金属层。 将半导体芯片放置在至少一些开口中。 在结构化金属层和半导体芯片上施加封装材料以形成封装体。 封装体被分离成多个电子器件封装。

公开(公告)号：US20150235890A1

公开(公告)日：2015-08-20

申请号：US14182689

申请日：2014-02-18

Applicant: Infineon Technologies AG

Inventor： Bernhard Goller ,  Eva-Maria Hess ,  Edward Fuergut ,  Christian Schweiger

IPC: H01L21/683 ,  H01L21/268 ,  H01L21/762 ,  H01L23/00 ,  H01L21/78 ,  H01L21/304

CPC classification number: H01L21/6835 ,  H01L21/268 ,  H01L21/304 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76251 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/02 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/82106 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00 ,  H01L2224/82 ,  H05K3/467 ,  H01L2224/03 ,  H01L2924/01029

Abstract: A method for manufacturing a semiconductor device includes providing a carrier and a semiconductor wafer having a first side and a second side opposite to the first side. The method includes applying a dielectric material to the carrier or the semiconductor wafer and bonding the semiconductor wafer to the carrier via the dielectric material. The method includes processing the semiconductor wafer and removing the carrier from the semiconductor wafer such that the dielectric material remains on the semiconductor wafer to provide a semiconductor device comprising the dielectric material.

Abstract translation: 一种制造半导体器件的方法包括提供具有第一侧和与第一侧相对的第二侧的载流子和半导体晶片。 该方法包括将介电材料施加到载体或半导体晶片，并通过电介质材料将半导体晶片接合到载体上。 该方法包括处理半导体晶片并从半导体晶片去除载体，使得介电材料保留在半导体晶片上，以提供包括电介质材料的半导体器件。

公开(公告)号：US20150221523A1

公开(公告)日：2015-08-06

申请号：US14598288

申请日：2015-01-16

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/3213 ,  H01L21/283 ,  H01L27/02 ,  H01L21/306 ,  H01L23/498 ,  H01L21/56 ,  H01L21/304

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

Abstract translation: 提供了一种安排。 该布置可以包括：具有前侧和后侧的基板，基板内的管芯区域，限定管芯区域的背面的多用途层以及设置在多用途层之间的蚀刻停止层， 多用途层和背面。 多用途层可以由欧姆材料形成，并且蚀刻停止层可以是第一掺杂浓度的第一导电类型。

公开(公告)号：US20140167800A1

公开(公告)日：2014-06-19

申请号：US13715990

申请日：2012-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Edward Fuergut ,  Horst Groeninger

IPC: G01R31/26

CPC classification number: G01R31/2601

Abstract: A semiconductor chip panel includes a plurality of semiconductor chips embedded in an encapsulation material. At least part of the semiconductor chips comprise a first electrical contact element on a first main face and a second electrical contact element on a second main opposite to the first main face, respectively. One of the plurality of semiconductor chips is tested by establishing an electrical contact between a test contact device and the first electrical contact element and between an electrically conductive holder and the second contact element.

Abstract translation: 半导体芯片面板包括嵌入在封装材料中的多个半导体芯片。 半导体芯片的至少一部分分别包括在第一主面上的第一电接触元件和与第一主面相对的第二主体上的第二电接触元件。 通过在测试接触装置和第一电接触元件之间以及在导电保持器和第二接触元件之间建立电接触来测试多个半导体芯片中的一个。

公开(公告)号：US20140138843A1

公开(公告)日：2014-05-22

申请号：US13681079

申请日：2012-11-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Georg Meyer-Berg ,  Khalil Hosseini ,  Joachim Mahler ,  Edward Fuergut

IPC: H01L23/538 ,  H01L21/58 ,  H01L21/78

CPC classification number: H01L23/5384 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/00

Abstract: A carrier and a semiconductor chip are provided. A connection layer is applied to a first main face of the semiconductor chip. The connection layer includes a plurality of depressions. A filler is applied to the connection layer or to the carrier. The semiconductor chip is attached to the carrier so that the connection layer is disposed between the semiconductor chip and the carrier. The semiconductor chip is affixed to the carrier.

Abstract translation: 提供载体和半导体芯片。 连接层被施加到半导体芯片的第一主面。 连接层包括多个凹陷。 将填料施加到连接层或载体上。 将半导体芯片附着到载体上，使得连接层设置在半导体芯片和载体之间。 半导体芯片固定在载体上。