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    Methods of forming diodes
    92.
    发明授权
    Methods of forming diodes 有权

    公开(公告)号：US09276081B2

    公开(公告)日：2016-03-01

    申请号：US14543349

    申请日：2014-11-17

    Applicant: Micron Technology, Inc.

    Inventor： Gurtej S. Sandhu ,  Chandra Mouli

    IPC: H01L21/28 ,  H01L21/44 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/872 ,  H01L45/00 ,  H01L49/02

    Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

    Field Effect Transistor Constructions And Memory Arrays
    93.
    发明申请
    Field Effect Transistor Constructions And Memory Arrays 有权
    场效应晶体管结构和存储器阵列

    公开(公告)号：US20150200308A1

    公开(公告)日：2015-07-16

    申请号：US14519021

    申请日：2014-10-20

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

    IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66

    CPC classification number: H01L27/2454 ,  H01L21/02568 ,  H01L27/11582 ,  H01L27/2463 ,  H01L29/0603 ,  H01L29/24 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/66969 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696 ,  H01L29/7926 ,  H01L45/065 ,  H01L45/141 ,  H01L45/16

    Abstract: In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers.

    Abstract translation: 在一些实施例中，晶体管包括具有底部源极/漏极区域，第一绝缘材料，导电栅极，第二绝缘材料和顶部源极/漏极区域的堆叠。 该堆叠具有沿底部源极/漏极区域具有底部的垂直侧壁，沿着导电栅极的中间部分和沿着顶部源极/漏极区域的顶部部分。 第三绝缘材料沿着垂直侧壁的中间部分。 沟道区域材料沿着第三绝缘材料。 通道区域材料直接抵靠垂直侧壁的顶部和底部。 沟道区域材料的厚度在大于约至小于或等于的范围内; 和/或具有1个单层至7个单层的厚度。

    VERTICAL MEMORY CELL STRING WITH DIELECTRIC IN A PORTION OF THE BODY
    95.
    发明申请
    VERTICAL MEMORY CELL STRING WITH DIELECTRIC IN A PORTION OF THE BODY 有权
    垂直存储单元，具有介电体部分

    公开(公告)号：US20150108560A1

    公开(公告)日：2015-04-23

    申请号：US14581774

    申请日：2014-12-23

    Applicant: Micron Technology, Inc.

    Inventor： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

    IPC: H01L27/115

    CPC classification number: H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    Abstract: Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

    Abstract translation: 一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质 源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。 身体部分中的电介质不会沿着身体的整个长度延伸。 描述和要求保护其他实施例。

    Memory cells, memory cell constructions, and memory cell programming methods
    96.
    发明授权
    Memory cells, memory cell constructions, and memory cell programming methods 有权
    存储单元，存储单元构造和存储单元编程方法

    公开(公告)号：US08871574B2

    公开(公告)日：2014-10-28

    申请号：US13959511

    申请日：2013-08-05

    Applicant: Micron Technology, Inc.

    Inventor： Chandra Mouli

    IPC: H01L21/20 ,  H01L45/00 ,  G11C13/00 ,  G11C11/02 ,  H01L27/102 ,  H01L27/10 ,  H01L27/24

    CPC classification number: H01L45/145 ,  G11C11/02 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2418 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

    Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

    Abstract translation: 一些实施例包括存储单元，其包括在第一导电材料和第二导电材料之间具有第一导电材料，第二导电材料和氧化物材料的存储元件。 存储器组件的电阻可以通过从第一导电材料通过氧化物材料传导到第二导电材料的电流来配置。 其他实施例包括包含金属和介电材料的二极管以及与二极管串联连接的存储器组件。 存储器部件包括磁阻材料，并且具有可以经由二极管和磁阻材料传导的电流而变化的电阻。

    Transistors Comprising a SiC-Containing Channel
    98.
    发明申请
    Transistors Comprising a SiC-Containing Channel 有权
    包含含SiC通道的晶体管

    公开(公告)号：US20130248885A1

    公开(公告)日：2013-09-26

    申请号：US13901719

    申请日：2013-05-24

    Applicant: Micron Technology, Inc.

    Inventor： Chandra Mouli

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66666 ,  H01L21/8213 ,  H01L27/105 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10879 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/785 ,  Y10S438/931

    Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.

    Abstract translation: 存储器件包括存储器单元阵列和外围设备。 至少一些单独的记忆单元包括含有SiC的碳酸化部分。 至少一些外围设备不包括任何碳酸化部分。 晶体管包括第一源极/漏极，第二源极/漏极，包括在第一和第二源极/漏极之间包含SiC的半导体衬底的碳酸化部分的沟道以及与沟道的相对侧可操作地相关联的栅极。

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