公开(公告)号：US07765074B2

公开(公告)日：2010-07-27

申请号：US11445702

申请日：2006-06-02

Applicant: Dennis Kim ,  Jared Zerbe ,  Mark Horowitz ,  William Stonecypher

Inventor： Dennis Kim ,  Jared Zerbe ,  Mark Horowitz ,  William Stonecypher

IPC: G06F19/00

CPC classification number: H03L7/0814 ,  H03L7/091 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/044 ,  H04L7/10

Abstract: A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.

Abstract translation: 电路，装置和方法使用相移数据采样时钟在接收电路获得系统余量，同时允许CDR在实施例中与输入数据流保持同步。 在一个实施例中，电路包括第一和第二采样器，用于对数据信号进行采样，并响应于数据时钟信号和边沿时钟信号输出数据和边缘信息。 相位检测器响应于数据信息和边缘信息产生相位信息。 时钟相位调整电路在同步模式期间响应于数据信息产生数据时钟信号和边沿时钟信号。 时钟相位调整电路在波形捕获模式期间递增数据时钟信号的相位。

公开(公告)号：US20100025811A1

公开(公告)日：2010-02-04

申请号：US12516499

申请日：2007-11-29

Applicant: Gary Bronner ,  Brent S. Haukness ,  Fariborz Assaderaghi ,  Mark D. Kellam ,  Mark Horowitz

Inventor： Gary Bronner ,  Brent S. Haukness ,  Fariborz Assaderaghi ,  Mark D. Kellam ,  Mark Horowitz

IPC: H01L23/34

CPC classification number: H01L27/105 ,  H01L21/67103 ,  H01L23/345 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit device (100) includes structures (104) that exhibit performance degradation as a function of use (e.g., accumulated defects within the tunneling oxide of a Flash memory cell, or trapped charge within a charge storage layer) and heating circuitry (101) disposed in proximity to the structures to heat the structures to a temperature that reverses the degradation. The word lines or the bit lines of the memory device are used as heating elements (107).

Abstract translation: 集成电路装置（100）包括结构（104），其显示作为使用功能的性能劣化（例如，闪存单元的隧穿氧化物内的累积缺陷或电荷存储层内的俘获电荷）和加热电路（101 ）设置在结构附近，以将结构加热到降低退化的温度。 存储器件的字线或位线用作加热元件（107）。

公开(公告)号：US07308044B2

公开(公告)日：2007-12-11

申请号：US10673677

申请日：2003-09-30

Applicant: Jared LeVan Zerbe ,  Grace Tsang ,  Mark Horowitz ,  Bruno Werner Garlepp ,  Carl William Werner

Inventor： Jared LeVan Zerbe ,  Grace Tsang ,  Mark Horowitz ,  Bruno Werner Garlepp ,  Carl William Werner

IPC: H04L27/06

CPC classification number: H04L25/4917

Abstract: A technique for receiving differential multi-PAM signals is disclosed. In one particular exemplary embodiment, the technique may be realized as a differential multi-PAM extractor circuit. In this particular exemplary embodiment, the differential multi-PAM extractor circuit comprises an upper LSB sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal. The differential multi-PAM extractor circuit also comprises a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal. The differential multi-PAM extractor circuit further comprises a combiner circuit configured to receive the first differential sampled output signal and the second differential sampled output signal, and to generate a differential LSB output signal indicating an LSB value of the differential multi-PAM input signal.

Abstract translation: 公开了一种用于接收差分多PAM信号的技术。 在一个特定的示例性实施例中，该技术可以被实现为差分多PAM提取器电路。 在该特定示例性实施例中，差分多PAM提取器电路包括被配置为接收差分多PAM输入信号和第一差分参考信号的高LSB采样器电路，并且产生第一差分采样输出信号。 差分多PAM提取器电路还包括被配置为接收差分多PAM输入信号和第二差分参考信号的低LSB采样器电路，并且产生第二差分采样输出信号。 差分多PAM提取器电路还包括组合器电路，其被配置为接收第一差分采样输出信号和第二差分采样输出信号，并且产生指示差分多PAM输入信号的LSB值的差分LSB输出信号。

公开(公告)号：US20070030342A1

公开(公告)日：2007-02-08

申请号：US11187699

申请日：2005-07-21

Applicant: Bennett Wilburn ,  Neel Joshi ,  Marc Levoy ,  Mark Horowitz

Inventor： Bennett Wilburn ,  Neel Joshi ,  Marc Levoy ,  Mark Horowitz

IPC: H04N13/02

CPC classification number: H04N5/247 ,  H04N5/3532 ,  H04N5/357

Abstract: This invention relates to an apparatus and a method for video capture of a three-dimensional region of interest in a scene using an array of video cameras. The video cameras of the array are positioned for viewing the three-dimensional region of interest in the scene from their respective viewpoints. A triggering mechanism is provided for staggering the capture of a set of frames by the video cameras of the array. The apparatus has a processing unit for combining and operating on the set of frames captured by the array of cameras to generate a new visual output, such as high-speed video or spatio-temporal structure and motion models, that has a synthetic viewpoint of the three-dimensional region of interest. The processing involves spatio-temporal interpolation for determining the synthetic viewpoint space-time trajectory. In some embodiments, the apparatus computes a multibaseline spatio-temporal optical flow.

Abstract translation: 本发明涉及使用摄像机阵列在场景中对三维感兴趣区域进行视频采集的装置和方法。 阵列的摄像机被定位成从它们各自的视点观看场景中的感兴趣的三维区域。 提供了一种触发机制，用于通过阵列的摄像机交错捕获一组帧。 该装置具有处理单元，用于组合并操作由相机阵列捕获的一组帧，以产生新的视觉输出，例如高速视频或时空结构和运动模型，其具有合成视点 感兴趣的三维区域。 该处理涉及用于确定合成视点时空轨迹的时空插值。 在一些实施例中，该装置计算多基线时空光流。

公开(公告)号：US20060188051A1

公开(公告)日：2006-08-24

申请号：US11406557

申请日：2006-04-18

Applicant: Kevin Donnelly ,  Pak Chau ,  Mark Horowitz ,  Thomas Lee ,  Mark Johnson ,  Benedict Lau ,  Leung Yu ,  Bruno Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Tran ,  Donald Stark ,  Nhat Nguyen

Inventor： Kevin Donnelly ,  Pak Chau ,  Mark Horowitz ,  Thomas Lee ,  Mark Johnson ,  Benedict Lau ,  Leung Yu ,  Bruno Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Tran ,  Donald Stark ,  Nhat Nguyen

IPC: H04L7/00

CPC classification number: H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

Abstract: A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.

Abstract translation: 适于耦合到数据总线并被配置为根据接收时钟接收数据的接收机包括第一和第二延迟锁定环路。 第一延迟锁定环路被配置为从第一参考时钟产生多个相位矢量，并且第二延迟锁定环路耦合到第一延迟锁定环路并且被配置为从至少一个相位矢量生成接收时钟 从所述多个相位矢量中选择并具有第二参考时钟。

公开(公告)号：US20050251602A1

公开(公告)日：2005-11-10

申请号：US11181411

申请日：2005-07-13

Applicant: Mark Horowitz ,  Richard Barth ,  Craig Hampel ,  Alfredo Moncayo ,  Kevin Donnelly ,  Jared Zerbe

Inventor： Mark Horowitz ,  Richard Barth ,  Craig Hampel ,  Alfredo Moncayo ,  Kevin Donnelly ,  Jared Zerbe

IPC: G06F13/00 ,  G06F13/40 ,  H03K19/003 ,  H03K19/0185

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device is described. The integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored in a supplemental memory device.

Abstract translation: 描述集成电路器件。 集成电路装置包括具有用于输出数据的输出驱动器的发送器电路和用于存储表示输出驱动器的均衡均衡设置的值的寄存器。 该值可以基于存储在补充存储器件中的信息来确定。

公开(公告)号：US20050149659A1

公开(公告)日：2005-07-07

申请号：US11073403

申请日：2005-03-04

Applicant: Mark Horowitz ,  Richard Barth ,  Craig Hampel ,  Alfredo Moncayo ,  Kevin Donnelly ,  Jared Zerbe

Inventor： Mark Horowitz ,  Richard Barth ,  Craig Hampel ,  Alfredo Moncayo ,  Kevin Donnelly ,  Jared Zerbe

IPC: G06F13/00 ,  G06F13/40 ,  H03K19/003 ,  H03K19/0185

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter, a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topography dependent parameter for later use by the parameter adjustment circuitry. The parameter adjustment circuitry adjusts a parameter control signal in accordance with the topography dependent parameter, which is coupled to the output driver. Prior to driving an output signal onto a bus, the output driver adjusts the transmit signal characteristic in accordance with the parameter control signal. Similarly, in a bus receiver, a receive signal characteristic is adjusted in response to a topography dependent parameter.

Abstract translation: 通过根据一个或多个地形相关参数调整信号特性来优化总线通信。 在总线发送器中，根据地形相关参数来调整发送信号特性。 总线发射器中的端口接收地形相关参数，供以后由参数调整电路使用。 参数调整电路根据与输出驱动器耦合的地形相关参数来调整参数控制信号。 在将输出信号驱动到总线之前，输出驱动器根据参数控制信号调整发送信号特性。 类似地，在总线接收器中，响应于地形相关参数来调整接收信号特性。

公开(公告)号：US20050141332A1

公开(公告)日：2005-06-30

申请号：US10973268

申请日：2004-10-27

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Abstract translation: 本发明包括一个包括至少两个半导体器件的存储器子系统，包括连接到总线的至少一个存储器件，其中总线包括用于承载所有存储器件所需的所有地址，数据和控制信息的多条总线 ，其中控制信息包括设备选择信息，并且总线具有比单个地址中的位数少得多的总线，并且总线承载设备选择信息，而不需要直接连接到各个设备的单独的设备选择线 。 本发明还包括用于主设备和从设备在总线上通信的协议，以及用于每个设备中的寄存器以区分每个设备并允许总线请求被引导到单个或所有设备的协议。 本发明包括对现有技术设备的修改，以允许它们实现本发明的新特征。 在一个优选实施方式中，8个总线数据线和一个AddressValid总线携带地址，数据和控制信息，用于高达40位宽的存储器地址。

公开(公告)号：US20050135489A1

公开(公告)日：2005-06-23

申请号：US10739823

申请日：2003-12-17

Applicant: Andrew Ho ,  Vladimir Stojanovic ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

Inventor： Andrew Ho ,  Vladimir Stojanovic ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

IPC: G06F13/40 ,  H03K19/003 ,  H04L5/20 ,  H04L12/56 ,  H04B3/00

CPC classification number: H04L47/10 ,  H04L5/20 ,  H04L25/0276

Abstract: Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily rejected by differential receivers, thus allowing for very high differential data rates. Some embodiments employ the common-mode signals to transmit backchannel signals for adjusting the characteristics of the differential transmitter. Backchannel control signals are effectively conveyed even if the forward channel transmitter is so maladjusted that the received differential data is unrecognizable. Systems in accordance with the above-described embodiments obtain these advantages without additional pins or communications channels, and are compatible with both AC-coupled and DC-coupled communications channels. Data coding schemes and corresponding data recovery circuits eliminate the need for complex, high-speed CDR circuits.

Abstract translation: 描述了通过相同的差分通道传送差分和共模信号的通信系统。 耐噪声通信方案使用容易被差分接收机拒绝的低振幅共模信号，从而允许非常高的差分数据速率。 一些实施例采用共模信号来发送用于调整差分发射机的特性的反向信道信号。 即使前向信道发射机被调整不正确，接收到的差分数据是无法识别的，反向信道控制信号也被有效地传送。 根据上述实施例的系统在没有附加引脚或通信信道的情况下获得这些优点，并且与AC耦合和DC耦合通信信道兼容。 数据编码方案和相应的数据恢复电路不需要复杂的高速CDR电路。

公开(公告)号：US20050134306A1

公开(公告)日：2005-06-23

申请号：US10851505

申请日：2004-05-21

Applicant: Vladimir Stojanovic ,  Andrew Ho ,  Anthony Bessios ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

Inventor： Vladimir Stojanovic ,  Andrew Ho ,  Anthony Bessios ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

IPC: H03K19/003 ,  H04L25/02 ,  H04L25/03 ,  H04L25/06 ,  H04L25/49

CPC classification number: H04L25/49 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0416 ,  H04L25/025 ,  H04L25/028 ,  H04L25/0282 ,  H04L25/03019 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/061 ,  H04L25/4917 ,  H04L2025/03363 ,  H04L2025/03802

Abstract: A signaling system having an equalizing transmitter and equalizing receiver. The equalizing transmitter transmits a signal to a receive circuit. A first sampling circuit within the equalizing receiver samples the signal to determine whether the signal exceeds a first threshold, and a second sampling circuit within the equalizing receiver samples the signal to determine whether the signal exceeds a second threshold. A drive strength of the equalizing transmitter and a drive strength of an equalizing signal driver within the equalizer are adjusted based, at least in part, on whether the first signal exceeds the first and second thresholds.

Abstract translation: 一种具有均衡发射机和均衡接收机的信令系统。 均衡发射机将信号发送到接收电路。 均衡接收器内的第一采样电路对信号进行采样以确定信号是否超过第一阈值，并且均衡接收器内的第二采样电路对信号进行采样以确定信号是否超过第二阈值。 至少部分地基于第一信号是否超过第一和第二阈值来调整均衡器的驱动强度和均衡器内均衡信号驱动器的驱动强度。