公开(公告)号：US20180166120A1

公开(公告)日：2018-06-14

申请号：US15829787

申请日：2017-12-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Zhichao Lu ,  Kenneth Lee Wright

IPC: G11C11/4091 ,  G06F11/10

Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

公开(公告)号：US09997233B1

公开(公告)日：2018-06-12

申请号：US15285974

申请日：2016-10-05

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/10 ,  G06F12/14 ,  G06F13/16

CPC classification number: G11C11/4093 ,  G06F12/1433 ,  G06F13/1673 ,  G06F13/1678 ,  G06F2212/1052 ,  G11C5/04 ,  G11C7/1072 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C29/22 ,  G11C29/32 ,  G11C29/38

Abstract: In a memory module having a buffer component, a plurality of data signaling paths and a plurality of memory dies each coupled to a respective one of the data signaling paths, the buffer component receives and stores a first configuration value that specifies a memory-die quantity N, where N is permitted to range from a first value corresponding to the quantity of the data signaling paths to at least one value less than the first value. The buffer component further receives a memory read command and enables, in accordance with the first configuration value, a quantity N of the memory dies to output read data in response to the memory read command.

公开(公告)号：US09979416B2

公开(公告)日：2018-05-22

申请号：US14941564

申请日：2015-11-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: H03M13/05 ,  G06F13/16 ,  G06F3/06 ,  H03M13/09 ,  H03M13/11 ,  H03M13/15 ,  H03M13/19

CPC classification number: H03M13/05 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0673 ,  G06F13/1668 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/19

Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

公开(公告)号：US09959914B2

公开(公告)日：2018-05-01

申请号：US15169331

申请日：2016-05-31

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Frederick A. Ware

IPC: G06F13/16 ,  G11C7/10 ,  G11C5/06

CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/1694 ,  G11C5/06 ,  G11C7/1045 ,  G11C7/1075

Abstract: A memory system includes a memory controller with multiple command/address ports and a memory device having corresponding request ports. The memory controller issues commands to memory device to cause the memory device to “loop-back” signals conveyed to memory device over one of the command/address ports via a bidirectional data link; these signals can be deterministic test patterns. The memory controller compares the returned information with the originally transmitted patterns to perform calibration. In one embodiment, because the return links are already calibrated, errors can be attributed to issues in the forward links; the memory controller then adjusts timing of the forward links to minimize the errors.

公开(公告)号：US09941005B2

公开(公告)日：2018-04-10

申请号：US15338872

申请日：2016-10-31

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Gary Bela Bronner ,  Frederick A. Ware

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

公开(公告)号：US20180082884A1

公开(公告)日：2018-03-22

申请号：US15824762

申请日：2017-11-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

IPC: H01L21/768 ,  H01L25/065

Abstract: This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.

公开(公告)号：US09911468B2

公开(公告)日：2018-03-06

申请号：US15390674

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C7/10 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20170371740A1

公开(公告)日：2017-12-28

申请号：US15646025

申请日：2017-07-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F11/10 ,  G06F12/02 ,  G11C29/52

Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

公开(公告)号：US09824779B2

公开(公告)日：2017-11-21

申请号：US14717048

申请日：2015-05-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Vlad Fruchter ,  Chi-Ming Yeung

IPC: G11C29/00 ,  G11C29/56 ,  G06F11/07 ,  G06F3/06 ,  G11C29/44 ,  G06F11/10 ,  G11C29/52 ,  G11C5/04 ,  G11C11/401

CPC classification number: G11C29/765 ,  G06F3/0629 ,  G06F11/0751 ,  G06F11/1008 ,  G11C5/04 ,  G11C11/401 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/56008 ,  G11C29/88 ,  G11C2029/4402

Abstract: In response to a first memory access transaction having a first base address, data fields and a repair fields are retrieved from a first DRAM channel. The data fields include a first data field. The repair fields include a first repair field storing repair data. The repair data is to replace any data in the first data field. In response to a second memory access transaction having a second base address, repair tag fields are retrieved from a second DRAM channel. The repair tag fields include a repair tag field that indicates the repair data is be replace the data stored in the first data field.

公开(公告)号：US20170330610A1

公开(公告)日：2017-11-16

申请号：US15483817

申请日：2017-04-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G11C7/10 ,  G06F13/16 ,  G06F12/06 ,  G11C5/04 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/22

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.