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    Clock Generation for Timing Communications with Ranks of Memory Devices
    91.
    发明申请
    Clock Generation for Timing Communications with Ranks of Memory Devices 有权

    公开(公告)号：US20210049118A1

    公开(公告)日：2021-02-18

    申请号：US16921061

    申请日：2020-07-06

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

    IPC: G06F13/16 ,  G06F1/10 ,  G11C7/22 ,  G06F1/06 ,  G06F1/08 ,  G06F1/04

    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

    Semiconductor system
    92.
    发明授权
    Semiconductor system 有权

    公开(公告)号：US10804139B2

    公开(公告)日：2020-10-13

    申请号：US15824762

    申请日：2017-11-28

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

    IPC: H01L21/768 ,  H01L25/065

    Abstract: This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.

    Clock generation for timing communications with ranks of memory devices
    93.
    发明授权
    Clock generation for timing communications with ranks of memory devices 有权

    公开(公告)号：US10705990B2

    公开(公告)日：2020-07-07

    申请号：US16228695

    申请日：2018-12-20

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

    IPC: G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/16 ,  G11C7/22 ,  G11C7/04 ,  H04L7/033

    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

    Strobe acquisition and tracking
    94.
    发明授权
    Strobe acquisition and tracking 有权

    公开(公告)号：US10339990B2

    公开(公告)日：2019-07-02

    申请号：US15665312

    申请日：2017-07-31

    Applicant: Rambus Inc.

    Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

    IPC: G01C7/02 ,  G11C7/22 ,  G06F13/16 ,  G11C7/02

    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

    Memory controller with phase adjusted clock for performing memory operations
    95.
    发明授权
    Memory controller with phase adjusted clock for performing memory operations 有权

    公开(公告)号：US10249353B2

    公开(公告)日：2019-04-02

    申请号：US15604251

    申请日：2017-05-24

    Applicant: Rambus Inc.

    Inventor： Ian P. Shaeffer ,  Lei Luo

    IPC: G06F13/12 ,  G11C7/22 ,  G11C7/10 ,  G06F13/42 ,  G06F1/08 ,  G06F13/16 ,  G06F13/40

    Abstract: In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.

    ASYMMETRIC-CHANNEL MEMORY SYSTEM
    98.
    发明申请
    ASYMMETRIC-CHANNEL MEMORY SYSTEM 有权

    公开(公告)号：US20170249265A1

    公开(公告)日：2017-08-31

    申请号：US15458166

    申请日：2017-03-14

    Applicant: Rambus Inc.

    Inventor： Ian P. Shaeffer ,  Arun Vaidyanath ,  Sanku Mukherjee

    IPC: G06F13/16 ,  G06F1/32 ,  G06F13/40

    CPC classification number: G06F13/1678 ,  G06F1/3275 ,  G06F12/0246 ,  G06F13/1668 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A memory-control integrated circuit includes internal data conductors, steering circuitry and distinct first and second data interfaces, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, the steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.

    Error correction in a memory device
    100.
    发明授权
    Error correction in a memory device 有权
    存储器件中的错误校正

    公开(公告)号：US09575835B2

    公开(公告)日：2017-02-21

    申请号：US14692092

    申请日：2015-04-21

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang ,  Suresh N. Rajan ,  Ian P. Shaeffer ,  Frederick A. Ware ,  Wayne F. Ellis

    IPC: G06F11/10 ,  G11C29/44

    CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G06F11/108 ,  G11C11/40 ,  G11C29/24 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016

    Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

    Abstract translation: 动态随机存取存储器（DRAM）阵列被配置用于阵列的子集的选择性修复和纠错。 将纠错码（ECC）提供给阵列的选定子集，以保护检测到一个或多个弱存储器单元的行或部分行的存储单元。 通过向存储器阵列的边缘添加感测放大器条纹，阵列的相邻边缘段用于存储与阵列的受保护子集相关联的ECC信息。 位更换也适用于有缺陷的存储单元。 通过有选择地执行ECC而不是整个阵列，在面积和能量消耗方面，以阵列的最低成本保持存储器阵列的完整性。

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