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    Forwarding signal supply voltage in data transmission system
    92.
    发明授权
    Forwarding signal supply voltage in data transmission system 有权

    公开(公告)号：US09881652B2

    公开(公告)日：2018-01-30

    申请号：US15391744

    申请日：2016-12-27

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  John W. Poulton

    IPC: H04B15/00 ,  G11C5/14 ,  G06F11/07

    CPC classification number: G11C5/144 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0793 ,  G06F13/4072 ,  G11C5/145 ,  H04L1/203 ,  H04L25/0264 ,  H04L25/08

    Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

    Memory Systems, Modules, and Methods for Improved Capacity
    94.
    发明申请
    Memory Systems, Modules, and Methods for Improved Capacity 审中-公开

    公开(公告)号：US20170337014A1

    公开(公告)日：2017-11-23

    申请号：US15522164

    申请日：2015-11-04

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Scott C. Best

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/14

    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

    Memory with refresh logic to accommodate low-retention storage rows
    96.
    发明授权
    Memory with refresh logic to accommodate low-retention storage rows 有权
    具有刷新逻辑的内存，以适应低保留存储行

    公开(公告)号：US09390782B2

    公开(公告)日：2016-07-12

    申请号：US14306174

    申请日：2014-06-16

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ely Tsern

    IPC: G11C11/406 ,  G06F13/16

    CPC classification number: G11C11/406 ,  G06F13/1636 ,  G11C2211/4061

    Abstract: An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes normal-retention storage rows that exhibit retention times greater or equal to a first time interval, and having been tested to generate information identifying low-retention storage rows that exhibit retention times less than the first time interval. Refresh logic refreshes the normal-retention storage rows at a first refresh rate corresponding to the first time interval, and refreshes each low-retention storage row at a second refresh rate that is greater than the first refresh rate.

    Abstract translation: 公开了一种包括与存储器控制器芯片封装的存储器控​​制器芯片和存储器芯片的装置。 每个存储器芯片包括呈现大于或等于第一时间间隔的保持时间的正常保留存储行，并且已经被测试以生成标识低保留存储行的信息，其表现出小于第一时间间隔的保留时间。 刷新逻辑以对应于第一时间间隔的第一刷新速率刷新正常保留存储行，并且以大于第一刷新率的第二刷新率刷新每个低保留存储行。

    BUFFER CIRCUIT WITH DATA BIT INVERSION
    97.
    发明申请
    BUFFER CIRCUIT WITH DATA BIT INVERSION 有权
    缓冲电路与数据位反转

    公开(公告)号：US20160147481A1

    公开(公告)日：2016-05-26

    申请号：US14787651

    申请日：2014-04-25

    Applicant: RAMBUS INC.

    Inventor： Scott C. Best

    IPC: G06F3/06

    CPC classification number: G06F3/0656 ,  G06F3/0626 ,  G06F3/0673 ,  G11C5/04 ,  G11C7/1006

    Abstract: A buffer circuit (403) includes a primary interface (404), a secondary interface (405), and an encoder/decoder circuit (407A, 407B). The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

    Abstract translation: 缓冲电路（403）包括主接口（404），辅助接口（405）和编码器/解码器电路（407A，407B）。 主接口被配置为在n比特信道上通信，其中使用数据比特反转（DBI）对n比特信道上的n个并行比特进行编码。 辅助接口被配置为与多个m位通道上的多个集成电路器件进行通信，每个m位通道在不使用DBI的情况下传输m个并行位。 并且编码器/解码器电路被配置为在主接口的n位信道和辅助接口的多个m位信道之间转换数据字。

    Methods and circuits for dynamically scaling DRAM power and performance
    99.
    发明授权
    Methods and circuits for dynamically scaling DRAM power and performance 有权
    动态缩放DRAM功率和性能的方法和电路

    公开(公告)号：US09256376B2

    公开(公告)日：2016-02-09

    申请号：US14452373

    申请日：2014-08-05

    Applicant: Rambus Inc.

    Inventor： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

    IPC: G11C7/00 ,  G06F3/06 ,  G11C11/4074 ,  G06F1/26 ,  G11C5/14

    CPC classification number: G06F3/0625 ,  G06F1/266 ,  G06F3/0634 ,  G06F3/0673 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

    Abstract: A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

    Abstract translation: 内存系统支持高性能和低功耗模式。 存储器系统包括存储器核和核心接口。 存储器内核采用在两种模式下保持相同的核心电源电压。 核心接口的电源电压和信号速率可以缩小以节省功耗。 存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

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