公开(公告)号：US20180106863A1

公开(公告)日：2018-04-19

申请号：US15845339

申请日：2017-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Baher S. Haroun

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/26 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/26 ,  G01R31/31723 ,  G01R31/318505 ,  G01R31/318577

Abstract: This disclosure describes a novel .method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

公开(公告)号：US09880222B2

公开(公告)日：2018-01-30

申请号：US15176874

申请日：2016-06-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Baher S. Haroun

IPC: G01R31/3177 ,  G01R31/26 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/26 ,  G01R31/31723 ,  G01R31/318505 ,  G01R31/318577

Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

公开(公告)号：US20180017678A1

公开(公告)日：2018-01-18

申请号：US15638255

申请日：2017-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nirmal C. Warke ,  David P. Magee ,  Baher S. Haroun

IPC: G01S17/10 ,  H03F3/08 ,  G01S17/32

CPC classification number: G01S17/102 ,  G01S7/484 ,  G01S7/4861 ,  G01S17/10 ,  G01S17/325 ,  G01S17/36 ,  H03F3/08

Abstract: Described examples include an integrated circuit having an analog-to-digital converter operable to receive an input signal derived from a light signal and convert the input signal to a digital received signal, the analog-to-digital converter operable to receive the input signal during at least one window. The integrated circuit further has a receiver operable to receive the digital received signal, the receiver operable to determine a distance estimate of an object from which the light signal is reflected based on the digital received signal. In an example, the window locations are chosen to correspond to the locations of maximum slope in the signal.

公开(公告)号：US20170329010A1

公开(公告)日：2017-11-16

申请号：US15484975

申请日：2017-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nirmal C. Warke ,  David P. Magee ,  Baher S. Haroun

IPC: G01S17/10

Abstract: Described examples include an integrated circuit that includes an encoder configured to modulate a driving signal for an optical transmitter with a plurality of encoded pulses corresponding to a code, in which the driving signal is transmitted to the optical transmitter periodically. The integrated circuit also includes a demodulator configured to receive a received signal from an optical receiver that is configured to receive a reflection of light transmitted by the optical transmitter off an object, the demodulator configured to discriminate the plurality of encoded pulses in the received signal and estimate a distance of the object.

公开(公告)号：US20170328993A1

公开(公告)日：2017-11-16

申请号：US15485147

申请日：2017-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nirmal C. Warke ,  David P. Magee ,  Baher S. Haroun

IPC: G01S7/491 ,  G01S7/484 ,  G01S7/493 ,  G01S17/36

CPC classification number: G01S7/4911 ,  G01S7/484 ,  G01S7/487 ,  G01S7/493 ,  G01S17/10 ,  G01S17/36

Abstract: Described example aspects include an integrated circuit includes a timing controller configured to select a selected time slot in a measurement period having a plurality of time slots and a transmit driver configured to provide a transmit signal in accordance with the selected time slot, in which the transmit signal is transmitted to an optical transmitter. The integrated circuit also includes a range estimator configured to receive a received signal after the selected time slot from an optical receiver that is configured to receive a reflection of light transmitted by the optical transmitter off an object, the range estimator configured to determine an estimated distance of the object based on the received signal.

公开(公告)号：US20170149386A1

公开(公告)日：2017-05-25

申请号：US14947424

申请日：2015-11-20

Applicant: Texas Instruments Incorporated

Inventor： Baher S. Haroun ,  Ali Kiaei ,  Kai Yiu Tam

IPC: H03B5/36 ,  H03L1/02

CPC classification number: H03B5/364 ,  H03B5/326 ,  H03K3/0231 ,  H03L1/02 ,  H03L7/085 ,  H03L7/099 ,  H03L2207/50

Abstract: The systems and methods of oscillator frequency tuning using a bulk acoustic wave resonator include a relaxation oscillator, a BAW oscillator, a frequency counter, and an adjustment module. The BAW oscillator provides an accurate time reference even over temperature changes. The BAW oscillator is turned on periodically and the relaxation oscillator is calibrated with the BAW oscillator. A temporary and periodic enablement of the BAW oscillator maintains a low current consumption. The frequency counter counts a number of full periods of the BAW oscillator that occur in one period of the relaxation oscillator. Since each frequency is known, the number of pulses of the BAW oscillator that should occur during one period of the relaxation oscillator is known. If the count is different from what should be counted, a correction may be made by adjusting an input parameter of the relaxation oscillator.

公开(公告)号：US20160013753A1

公开(公告)日：2016-01-14

申请号：US14329939

申请日：2014-07-12

Applicant: Texas Instruments Incorporated

Inventor： Kai Yiu Tam ,  Ali Kiaei ,  Baher S. Haroun

IPC: H03B5/04 ,  H03K4/02 ,  H03B5/24 ,  H03K4/50

CPC classification number: H03B5/04 ,  H03B5/24 ,  H03K3/0231 ,  H03K4/023 ,  H03K4/50 ,  H03K4/502 ,  H03K4/94

Abstract: A relaxation oscillator reduces temperature sensitivity and phase noise at low offset frequency by periodically swapping a first current and a second current so that after the first current has been input to a first pair of circuits and the second current has been input to a second pair of circuits, the second current is input to the first pair of circuits and the first current is input to the second pair of circuits.

Abstract translation: 松弛振荡器通过周期性交换第一电流和第二电流来降低在低偏移频率下的温度灵敏度和相位噪声，使得在第一电流已经被输入到第一对电路之后，并且第二电流已经被输入到第二对 电路，第二电流被输入到第一对电路，第一电流被输入到第二对电路。

公开(公告)号：US20150280320A1

公开(公告)日：2015-10-01

申请号：US14734371

申请日：2015-06-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Baher S. Haroun ,  Marco Corsi ,  Siraj Akhtar ,  Nirmal C. Warke

IPC: H01Q3/44 ,  H01Q9/04 ,  H01Q3/26

CPC classification number: H01Q3/44 ,  H01L23/3107 ,  H01L23/66 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/3011 ,  H01Q3/26 ,  H01Q9/0407 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.

Abstract translation: 在一些开发的互连技术中，例如芯片到芯片的光学互连或金属波导互连，错位可能是一个严重的问题。 然而，这里提供了使用片上定向天线（其在亚毫米范围内操作）通过介质波导形成射频（RF）互连的互连。 该系统允许不对准，同时提供增加的通信带宽。

公开(公告)号：US20150260791A1

公开(公告)日：2015-09-17

申请号：US14728580

申请日：2015-06-02

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Vij

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract translation: IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

公开(公告)号：US09136796B2

公开(公告)日：2015-09-15

申请号：US13920302

申请日：2013-06-18

Applicant: Texas Instruments Incorporated

Inventor： David H. Elwart, II ,  Vikas Suma Vinay ,  Christopher M. Graves ,  Baher S. Haroun

IPC: H04B15/00 ,  H03F1/30 ,  H02H9/04

CPC classification number: H03F1/305 ,  H02H9/045 ,  H03F1/523 ,  H03F3/187 ,  H03F3/68 ,  H03F2200/441 ,  H03F2200/444 ,  H03F2200/555 ,  H03K17/6874 ,  H03K2217/0018

Abstract: Self-grounded circuitry (10) includes a signal channel conducting an output voltage (VOUT1). A charge pump (2) powered by a reference voltage (VDD) produces a control voltage (VCP). The control signal is at a low level if the reference voltage is low and is boosted to a high level if the reference voltage is high. A ground switch circuit (15) includes a depletion mode transistor (MP1) having a source coupled to the output voltage, a gate coupled to the control voltage, and a drain coupled to ground. The transistor includes a well region (4-1) and a parasitic substrate diode (D3-1). A negative voltage protection circuit (17-1) includes a depletion mode first protection transistor (MP3-1) having a drain coupled to the well region, a source coupled to a source of a depletion mode second protection transistor (MP4-1) having a drain coupled to the output voltage, the first and second protection transistors each having a gate coupled to the control voltage, and also includes a diode (MN1) coupled to charge the well region from the control voltage conductor to prevent distortion of the output voltage.

Abstract translation: 自接地电路（10）包括传导输出电压（VOUT1）的信号通道。 由参考电压（VDD）供电的电荷泵（2）产生控制电压（VCP）。 如果参考电压较低，则控制信号处于低电平，并且如果参考电压高，则其升压到高电平。 接地开关电路（15）包括具有耦合到输出电压的源极的耗尽型晶体管（MP1），耦合到控制电压的栅极和耦合到地的漏极。 晶体管包括阱区（4-1）和寄生衬底二极管（D3-1）。 负电压保护电路（17-1）包括具有耦合到阱区的漏极的耗尽型第一保护晶体管（MP3-1），耦合到耗尽型第二保护晶体管（MP4-1）的源极的源极， 耦合到输出电压的漏极，第一和第二保护晶体管各自具有耦合到控制电压的栅极，并且还包括耦合到从控制电压导体对阱区域充电的二极管（MN1），以防止输出电压的失真 。