公开(公告)号：US11798984B2

公开(公告)日：2023-10-24

申请号：US17588478

申请日：2022-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Chun Huang ,  Bor Chiuan Hsieh ,  Pei-Ren Jeng ,  Tai-Chun Huang ,  Tze-Liang Lee

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/76227 ,  H01L29/66795

Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

公开(公告)号：US20230317469A1

公开(公告)日：2023-10-05

申请号：US17711885

申请日：2022-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bor Chiuan Hsieh ,  Po-Hsien Cheng ,  Tsai-Jung Ho ,  Po-Cheng Shih ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L21/311 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/31144 ,  H01L21/76802 ,  H01L29/66795 ,  H01L29/6653 ,  H01L29/456 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76897

Abstract: A method of forming a semiconductor device includes forming a source/drain region over a substrate; forming a first interlayer dielectric over the source/drain region; forming a gate structure over the substrate and laterally adjacent to the source/drain region; and forming a gate mask over the gate structure, the forming the gate mask comprising: etching a portion of the gate structure to form a recess relative to a top surface of the first interlayer dielectric; depositing a first dielectric layer over the gate structure in the recess and over the first interlayer dielectric; etching a portion of the first dielectric layer; depositing a semiconductor layer over the first dielectric layer in the recess; and planarizing the semiconductor layer to be coplanar with the first interlayer dielectric. In another embodiment, the method further includes forming a gate spacer over the substrate, wherein the etching the portion of the gate structure further comprises etching a portion of the gate spacer.

公开(公告)号：US11676852B2

公开(公告)日：2023-06-13

申请号：US17119692

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Shing-Chyang Pan ,  Ching-Yu Chang ,  Wan-Lin Tsai ,  Jung-Hau Shiu ,  Tze-Liang Lee

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L21/76802 ,  H01L21/0228 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76879

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

公开(公告)号：US20230154750A1

公开(公告)日：2023-05-18

申请号：US17674575

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Chih-Cheng Liu ,  Yi-Chen Kuo ,  Yen-Yu Chen ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/027 ,  G03F7/40

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/0276 ,  G03F7/405

Abstract: Photoresists and methods of forming and using the same are disclosed. In an embodiment, a method includes spin-on coating a first hard mask layer over a target layer; depositing a photoresist layer over the first hard mask layer using chemical vapor deposition or atomic layer deposition, the photoresist layer being deposited using one or more organometallic precursors; heating the photoresist layer to cause cross-linking between the one or more organometallic precursors; exposing the photoresist layer to patterned energy; heating the photoresist layer to cause de-crosslinking in the photoresist layer forming a de-crosslinked portion of the photoresist layer; and removing the de-crosslinked portion of the photoresist layer.

公开(公告)号：US20230043635A1

公开(公告)日：2023-02-09

申请号：US17654627

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Chia-Ming Hsu ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L23/522

Abstract: A method includes forming a gate structure over a substrate; forming a source/drain region adjacent the gate structure; forming a first interlayer dielectric (ILD) over the source/drain region; forming a contact plug extending through the first ILD that electrically contacts the source/drain region; forming a silicide layer on the contact plug; forming a second ILD extending over the first ILD and the silicide layer; etching an opening extending through the second ILD and the silicide layer to expose the contact plug, wherein the silicide layer is used as an etch stop during the etching of the opening; and forming a conductive feature in the opening that electrically contacts the contact plug.

公开(公告)号：US11482411B2

公开(公告)日：2022-10-25

申请号：US16916499

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Chang ,  Jei Ming Chen ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/308 ,  H01L21/3065

Abstract: A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask.

公开(公告)号：US11437515B2

公开(公告)日：2022-09-06

申请号：US16925490

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Chii-Horng Li ,  Tze-Liang Lee

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

公开(公告)号：US20220246473A1

公开(公告)日：2022-08-04

申请号：US17524830

申请日：2021-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Hong Lu ,  Tsai-Jung Ho ,  Bor Chiuan Hsieh ,  Po-Cheng Shih ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8234

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a metal gate over the fin, the metal gate being surround by a dielectric layer; etching the metal gate to reduce a height of the metal gate, where after the etching, a recess is formed over the metal gate between gate spacers of the metal gate; lining sidewalls and a bottom of the recess with a semiconductor material; filling the recess by forming a dielectric material over the semiconductor material; forming a mask layer over the metal gate, where a first opening of the mask layer is directly over a portion of the dielectric layer adjacent to the metal gate; removing the portion of the dielectric layer to form a second opening in the dielectric layer, the second opening exposing an underlying source/drain region; and filling the second opening with a conductive material.

公开(公告)号：US11328952B2

公开(公告)日：2022-05-10

申请号：US17099263

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chou ,  Chih-Chien Chi ,  Chung-Chi Ko ,  Yao-Jen Chang ,  Chen-Yuan Kao ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Tze-Liang Lee ,  Jun-Yi Ruan

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/84 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/08

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US20220123115A1

公开(公告)日：2022-04-21

申请号：US17193626

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L23/535

Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.