公开(公告)号：US20120015388A1

公开(公告)日：2012-01-19

申请号：US13166575

申请日：2011-06-22

Applicant: Takeshi Takagi ,  Toshikatsu Sakai ,  Chiaki Miyamoto ,  Takefumi Asami ,  Tatsuo Kamata ,  Takuya Yotani ,  Takayuki Oka

Inventor： Takeshi Takagi ,  Toshikatsu Sakai ,  Chiaki Miyamoto ,  Takefumi Asami ,  Tatsuo Kamata ,  Takuya Yotani ,  Takayuki Oka

IPC: C12Q1/54 ,  C12M1/40

CPC classification number: C12Q1/006 ,  G01N33/66 ,  G01N33/723 ,  G01N33/726

Abstract: The ionic strength of a diluent for preparing an analytical sample is set to be 0.06 to 0.16. The analytical sample prepared by using the diluent having the ionic strength within this range can be subjected to both for analyzing a first object in a test sample by electrode method and for analyzing a second object in the test sample by liquid chromatography method, and high-precision measurement can be attained. The analytical sample is especially useful for preparing a sample for measurement used both for measuring glucose concentration in a blood sample by enzyme electrode method and for measuring glycohemoglobin concentration in the blood sample by liquid chromatography method.

Abstract translation: 用于制备分析样品的稀释剂的离子强度设定为0.06至0.16。 通过使用离子强度在该范围内的稀释剂制备的分析样品可以通过电极法分析测试样品中的第一个物体，并通过液相色谱法分析测试样品中的第二个物体， 可以进行精度测量。 分析样品特别适用于制备用于通过酶电极法测量血液样品中的葡萄糖浓度并通过液相色谱法测量血液样品中的糖血红蛋白浓度的测量样品。

公开(公告)号：US20110318767A1

公开(公告)日：2011-12-29

申请号：US13159226

申请日：2011-06-13

Applicant: Takeshi Takagi ,  Koji Okumura

Inventor： Takeshi Takagi ,  Koji Okumura

IPC: C12Q1/54 ,  G01N27/30 ,  C12M1/34 ,  G01N33/66

CPC classification number: G01N33/66 ,  C12Q1/006 ,  G01N33/726

Abstract: A measurement of plasma glucose is carried out through the following steps, a sample preparation step (S101, S102) of preparing a measurement sample by hemolyzing hemocytes in blood, a step of measuring whole blood glucose (S103 to S105) of measuring a glucose concentration in whole blood with the measurement sample, and a step of calculating a liquid content ratio of whole blood (S109) of calculating a liquid content ratio of whole blood from a hemocyte/plasma ratio in the blood hemocyte and predetermined ratios of liquid components of hemocytes and of liquid components of plasma.

Abstract translation: 通过以下步骤进行血浆葡萄糖的测定，通过血液中的血细胞溶血来制备测定试样的样品制备工序（S101，S102），测定全血的葡萄糖浓度的步骤（S103〜S105） 与测量样品的全血中，计算全血中的液体含有比例（S109），从血细胞中的血细胞/血浆比计算全血的液体含有率和血细胞的液体成分的预定比例 和等离子体的液体成分。

公开(公告)号：US20110244645A1

公开(公告)日：2011-10-06

申请号：US13162310

申请日：2011-06-16

Applicant: Junko IWANAGA ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

Inventor： Junko IWANAGA ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

Abstract translation: 一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US08022502B2

公开(公告)日：2011-09-20

申请号：US12307211

申请日：2008-03-26

Applicant: Yoshihiko Kanzawa ,  Koji Katayama ,  Satoru Fujii ,  Shunsaku Muraoka ,  Koichi Osano ,  Satoru Mitani ,  Ryoko Miyanaga ,  Takeshi Takagi ,  Kazuhiko Shimakawa

Inventor： Yoshihiko Kanzawa ,  Koji Katayama ,  Satoru Fujii ,  Shunsaku Muraoka ,  Koichi Osano ,  Satoru Mitani ,  Ryoko Miyanaga ,  Takeshi Takagi ,  Kazuhiko Shimakawa

IPC: H01L47/00

CPC classification number: H01L27/101 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675 ,  Y10S438/90

Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0

Abstract translation: 非易失性存储元件包括设置在第一电极层（103）和第二电极层（107）之间的第一电极层（103），第二电极（107）和电阻变化层（106），电阻 电阻变化层的值根据施加在电极（103），（107）之间的具有不同极性的电信号而可逆地变化，其中电阻变化层（106）具有第一区域，该第一区域包括第一氧缺陷型氧化钽， 由TaOx（0

公开(公告)号：US20110186511A1

公开(公告)日：2011-08-04

申请号：US13122602

申请日：2009-10-06

Applicant: Toshikatsu Sakai ,  Akira Sezaki ,  Takeshi Takagi ,  Takuya Yotani ,  Makoto Takahara ,  Takayuki Oka

Inventor： Toshikatsu Sakai ,  Akira Sezaki ,  Takeshi Takagi ,  Takuya Yotani ,  Makoto Takahara ,  Takayuki Oka

IPC: B01D15/08

CPC classification number: G01N30/24 ,  B01D15/16 ,  G01N30/26 ,  G01N30/34 ,  G01N30/74 ,  G01N2030/201 ,  G01N2030/202 ,  G01N2030/207 ,  G01N2030/8822

Abstract: A liquid chromatography apparatus is provided with a sample preparation unit, a column that separates components of a sample, an eluent supplier that includes a feeder for supplying eluents to the column, a flow path directional valve capable of introducing fixed amounts of the sample and the eluents to the column, an analyzer for analyzing a test solution composed of the sample components separated by the column and one of the eluents, and a controller, wherein the eluent supplier supplies the eluents to the flow path directional valve in an unmixed state. As a result of employing this configuration, analysis time is shortened and eluent consumption is reduced.

Abstract translation: 液相色谱装置具有样品制备单元，分离样品组分的柱，包括用于向柱供给洗脱液的供给器的洗脱液供给器，能够引入固定量的样品的流路切换阀和 用于分析由柱分离的样品组分和洗脱液之一组成的测试溶液的分析器和控制器，其中洗脱剂供体以未混合的状态将洗脱液供应到流路换向阀。 由于采用这种结构，分析时间缩短，洗脱液消耗减少。

公开(公告)号：US20110179856A1

公开(公告)日：2011-07-28

申请号：US13121878

申请日：2009-10-02

Applicant: Takafumi Aono ,  Takeshi Takagi

Inventor： Takafumi Aono ,  Takeshi Takagi

IPC: G01N30/38

CPC classification number: G01N30/20 ,  G01F23/292 ,  G01N30/26 ,  G01N2030/201 ,  G01N2030/202 ,  G01N2030/207

Abstract: A liquid chromatography device includes a column containing a filler, an injection valve capable of introducing a sample into the column and also capable of introducing a liquid mobile phase into the column, and a mobile phase feeder for feeding the liquid mobile phase from a mobile phase container containing the liquid mobile phase to the column via the injection valve. Between the mobile phase container and the injection valve is provided a storage chamber for temporarily storing the liquid mobile phase sent from the mobile phase container. The device further includes a liquid level detection sensor for detecting the liquid level of the liquid mobile phase in the storage chamber. This structure allows the liquid for use in analysis to be used completely without being wasted.

Abstract translation: 液相色谱装置包括含有填料的柱，能够将样品引入柱中并且还能够将液体流动相引入柱的喷射阀，以及流动相进料器，用于从流动相 通过注射阀将液体流动相装入柱的容器。 在流动相容器和喷射阀之间设置有用于临时存储从流动相容器发送的液体流动相的储存室。 该装置还包括用于检测储存室中的液体流动相的液位的液面检测传感器。 这种结构允许在分析中使用的液体被完全使用而不被浪费。

公开(公告)号：US07986002B2

公开(公告)日：2011-07-26

申请号：US10549291

申请日：2004-03-19

Applicant: Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

Inventor： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

IPC: H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

Abstract translation: 一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US07981760B2

公开(公告)日：2011-07-19

申请号：US12669812

申请日：2009-05-07

Applicant: Yoshio Kawashima ,  Takumi Mikawa ,  Takeshi Takagi ,  Koji Arita

Inventor： Yoshio Kawashima ,  Takumi Mikawa ,  Takeshi Takagi ,  Koji Arita

IPC: H01L21/00

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

Abstract: A method for manufacturing a nonvolatile storage element that minimizes shape shift between an upper electrode and a lower electrode, and which includes: depositing, in sequence, a connecting electrode layer which is conductive, a lower electrode layer and a variable resistance layer which are made of a non-noble metal nitride and are conductive, an upper electrode layer made of noble metal, and a mask layer; forming the mask layer into a predetermined shape; forming the upper electrode layer, the variable resistance layer, and the lower electrode layer into the predetermined shape by etching using the mask layer as a mask; and removing, simultaneously, the mask and a region of the connecting electrode layer that has been exposed by the etching.

Abstract translation: 一种用于制造使上部电极和下部电极之间的形状偏移最小化的非易失性存储元件的方法，包括：依次沉积导电的连接电极层，下部电极层和可变电阻层 的非贵金属氮化物，并且是导电的，由贵金属制成的上电极层和掩模层; 将掩模层形成为预定形状; 通过使用掩模层作为掩模通过蚀刻将上电极层，可变电阻层和下电极层形成为预定形状; 并且同时去除已经通过蚀刻暴露的掩模和连接电极层的区域。

公开(公告)号：US07960770B2

公开(公告)日：2011-06-14

申请号：US12445380

申请日：2007-10-12

Applicant: Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

Inventor： Takumi Mikawa ,  Takeshi Takagi ,  Yoshio Kawashima ,  Koji Arita

IPC: H01L29/76

CPC classification number: H01L27/101 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1683

Abstract: A lower electrode (22) is provided on a semiconductor chip substrate (26). A lower electrode (22) is covered with a first interlayer insulating layer (27) from above. A first contact hole (28) is provided on the lower electrode (22) to penetrate through the first interlayer insulating layer (27). A low-resistance layer (29) forming the resistance variable layer (24) is embedded to fill the first contact hole (28). A high-resistance layer (30) is provided on the first interlayer insulating layer (27) and the low-resistance layer (29). The resistance variable layer (24) is formed by a multi-layer resistance layer including a single layer of the high-resistance layer (30) and a single layer of the low-resistance layer (29). The low-resistance layer (29) forming the memory portion (25) is isolated from at least its adjacent memory portion (25).

Abstract translation: 下电极（22）设置在半导体芯片基板（26）上。 下部电极（22）从上方被第一层间绝缘层（27）覆盖。 第一接触孔（28）设置在下电极（22）上以穿透第一层间绝缘层（27）。 嵌入形成电阻变化层（24）的低电阻层（29），以填充第一接触孔（28）。 在第一层间绝缘层（27）和低电阻层（29）上设置有高电阻层（30）。 电阻变化层（24）由包含单层高电阻层（30）和单层低电阻层（29）的多层电阻层形成。 形成存储器部分（25）的低电阻层（29）至少与其相邻的存储器部分（25）隔离。

公开(公告)号：US07915656B2

公开(公告)日：2011-03-29

申请号：US12446964

申请日：2007-10-22

Applicant: Takumi Mikawa ,  Takeshi Takagi

Inventor： Takumi Mikawa ,  Takeshi Takagi

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/20

CPC classification number: H01L27/101 ,  H01L27/24

Abstract: A nonvolatile semiconductor memory apparatus (10) of the present invention comprises a semiconductor substrate (11), an active element forming region provided on the semiconductor substrate (11) and including a plurality of active elements (12), a wire forming region which is provided on the active element forming region to electrically connect the active elements (12) and includes plural layers of semiconductor electrode wires (15, 16), a memory portion forming region (100) which is provided above the wire forming region and provided with memory portions (26) arranged in matrix, a resistance value of each of the memory portions changing according to electric pulses applied, and an oxygen barrier layer (17) which is provided between the memory portion forming region (100) and the wire forming region so as to extend continuously over at least an entire of the memory portion forming region (100).

Abstract translation: 本发明的非易失性半导体存储器件（10）包括半导体衬底（11），设置在半导体衬底（11）上并包括多个有源元件（12）的有源元件形成区域， 设置在有源元件形成区域上以电连接有源元件（12）并且包括多层半导体电极线（15,16），存储部形成区域（100），其设置在线形成区域的上方并设置有存储器 布置成矩阵的部分（26），每个存储部分的电阻值根据施加的电脉冲而变化，以及设置在存储部分形成区域（100）和线形成区域之间的氧阻挡层（17），从而 以在至少整个存储部分形成区域（100）上连续地延伸。