公开(公告)号：US20240296129A1

公开(公告)日：2024-09-05

申请号：US18659407

申请日：2024-05-09

申请人： Texas Instruments Incorporated

发明人： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC分类号： G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

CPC分类号： G06F12/128 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/082 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/603 ,  G06F2212/6032 ,  G06F2212/6042 ,  G06F2212/608 ,  G06F2212/62

摘要： A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

公开(公告)号：US12056050B2

公开(公告)日：2024-08-06

申请号：US18086501

申请日：2022-12-21

申请人： International Business Machines Corporation

发明人： Derek E. Williams ,  Luke Murray ,  Guy L. Guthrie ,  Hugh Shen

IPC分类号： G06F12/0802 ,  G06F9/54 ,  G06F12/10

CPC分类号： G06F12/0802 ,  G06F9/542 ,  G06F12/10 ,  G06F2212/603

摘要： A data processing system includes a master, a central request agent, and a plurality of snoopers communicatively coupled to a system fabric for communicating requests subject to retry. The master issues on the system fabric a multicast request intended for the plurality of snoopers. The central request agent receives the multicast request on the system fabric, assigns the multicast request to a particular state machine among a plurality of state machines in the central request agent, and provides the master a coherence response indicating successful completion of the multicast request. The central request agent repetitively issues on the system fabric a multicast request in association with a machine identifier identifying the particular state machine until a coherence response indicates the multicast request is successfully received by all of the plurality of snoopers.

公开(公告)号：US20240248620A1

公开(公告)日：2024-07-25

申请号：US18619046

申请日：2024-03-27

申请人： Micron Technology, Inc.

发明人： Shivam Swami ,  Kenneth Marion Curewitz

IPC分类号： G06F3/06 ,  G06F12/0804

CPC分类号： G06F3/0625 ,  G06F3/0634 ,  G06F3/068 ,  G06F12/0804 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/603

摘要： Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task. In response to determining that the performance capability is adequate, the controller changes a mode of operation of the memory system so that one or more resources of the second memory device are used to service the task.

公开(公告)号：US20240211398A1

公开(公告)日：2024-06-27

申请号：US18086501

申请日：2022-12-21

申请人： International Business Machines Corporation

发明人： Derek E. WILLIAMS ,  Luke MURRAY ,  Guy L. GUTHRIE ,  Hugh SHEN

IPC分类号： G06F12/0802 ,  G06F9/54 ,  G06F12/10

CPC分类号： G06F12/0802 ,  G06F9/542 ,  G06F12/10 ,  G06F2212/603

摘要： A data processing system includes a master, a central request agent, and a plurality of snoopers communicatively coupled to a system fabric for communicating requests subject to retry. The master issues on the system fabric a multicast request intended for the plurality of snoopers. The central request agent receives the multicast request on the system fabric, assigns the multicast request to a particular state machine among a plurality of state machines in the central request agent, and provides the master a coherence response indicating successful completion of the multicast request. The central request agent repetitively issues on the system fabric a multicast request in association with a machine identifier identifying the particular state machine until a coherence response indicates the multicast request is successfully received by all of the plurality of snoopers.

公开(公告)号：US20240095164A1

公开(公告)日：2024-03-21

申请号：US17945242

申请日：2022-09-15

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC分类号： G06F12/0802

CPC分类号： G06F12/0802 ,  G06F2212/603

摘要： Methods, apparatus, systems and articles of manufacture are disclosed to evict in a dual datapath victim cache system. An example apparatus includes a cache storage, a cache controller operable to receive a first memory operation and a second memory operation concurrently, comparison logic operable to identify if the first and second memory operations missed in the cache storage, and a replacement policy component operable to, when at least one of the first and second memory operations corresponds to a miss in the cache storage, reserve an entry in the cache storage to evict based on the first and second memory operations.

公开(公告)号：US20230393980A1

公开(公告)日：2023-12-07

申请号：US18085475

申请日：2022-12-20

申请人： APPLE INC.

发明人： Mohamadou A. Abdoulaye ,  Peter Cooper ,  Michael J. Ash ,  Davide Italiano ,  Nick Kledzik

IPC分类号： G06F12/0802 ,  G06F16/22

CPC分类号： G06F12/0802 ,  G06F16/2272 ,  G06F2212/603

摘要： Techniques may include receiving a first request for a conformance check for a conformance pair, the conformance pair include a variable type and a particular protocol. The first request can identifying a first pointer. The technique can include determining a conformance check result is not cached for the conformance pair using the first pointer. In response to determining that the conformance check result is not cached for a variable, the electronic device may include performing the conformance check for the conformance pair and storing a result of the conformance check in an index table in persistent memory in association with at least a portion of bits in the first pointer. The technique can include referencing the index table on subsequent requests for a conformance check.

公开(公告)号：US11722154B2

公开(公告)日：2023-08-08

申请号：US17193354

申请日：2021-03-05

申请人： The Aerospace Corporation

发明人： Eugene Grayver ,  Mark Kubiak

IPC分类号： H03M13/27 ,  G06F12/0813 ,  G06F17/18

CPC分类号： H03M13/2732 ,  G06F12/0813 ,  G06F17/18 ,  G06F2212/603 ,  H03M13/2782

摘要： High-throughput software-defined convolutional interleavers and de-interleavers are provided herein. In some examples, a method for generating convolutionally interleaved samples on a general purpose processor with cache is provided. Memory is represented as a three dimensional array, indexed by block number, row, and column. Input samples may be written to the cache according to an indexing scheme. Output samples may be generated every MN samples by reading out the samples from the cache in a transposed and vectorized order.

公开(公告)号：US11693774B2

公开(公告)日：2023-07-04

申请号：US17412225

申请日：2021-08-25

申请人： Micron Technology, inc.

发明人： Jiangang Wu ,  Jing Sang Liu ,  Jung Sheng Hoei ,  Kishore Kumar Muchherla ,  Mark Ish ,  Myoung Jun Go ,  Nolan Tran ,  Qisong Lin

IPC分类号： G06F12/00 ,  G06F12/0806

CPC分类号： G06F12/0806 ,  G06F2212/1024 ,  G06F2212/603

摘要： A method is described, which includes receiving, by a memory subsystem, a memory command targeted at a memory array; determining, by the memory subsystem, if the memory command is a high priority memory command; and determining if the memory subsystem is processing any non-high priority memory commands. The memory subsystem enables a read page cache mode for processing the memory command in response to determining that (1) the memory command is a high priority memory command and (2) the memory subsystem is not processing any non-high priority memory commands Thereafter, the memory subsystem processes the memory command using the read page cache mode.

公开(公告)号：US20190121724A1

公开(公告)日：2019-04-25

申请号：US16224498

申请日：2018-12-18

申请人： Micron Technology, Inc.

发明人： Jason T. Zawodny ,  Kyle B. Wheeler ,  Richard C. Murphy

IPC分类号： G06F12/02 ,  G06F15/78 ,  G11C11/408 ,  G11C7/06 ,  G06F12/0888 ,  G11C11/4096 ,  G11C7/10

CPC分类号： G06F12/0238 ,  G06F12/0888 ,  G06F15/7821 ,  G06F2212/202 ,  G06F2212/603 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4096

摘要： Apparatuses and methods related to a memory device as the store to program instructions are described. An apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry, is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.

公开(公告)号：US20190042450A1

公开(公告)日：2019-02-07

申请号：US15668016

申请日：2017-08-03

申请人： Micron Technology, Inc.

发明人： Robert M. Walker

IPC分类号： G06F12/0888 ,  G06F12/121

CPC分类号： G06F12/0888 ,  G06F12/0871 ,  G06F12/121 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/461 ,  G06F2212/466 ,  G06F2212/603

摘要： The present disclosure includes apparatuses and methods related to a memory system including a filter. An example apparatus can include a filter to store a number flags, wherein each of the number of flags corresponds to a cache entry and each of the number of flags identifies a portion of the memory device where data of a corresponding cache entry is stored in the memory device.