公开(公告)号：US09887141B2

公开(公告)日：2018-02-06

申请号：US15491941

申请日：2017-04-19

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Peng Du ,  Cheng-hung Chen

IPC: H01L29/10 ,  H01L21/66 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L22/34 ,  H01L22/14 ,  H01L27/1244 ,  H01L27/127 ,  H01L29/66742 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/78696

Abstract: A thin-film transistor (TFT) switch includes a gate, a drain, a source, a semiconductor layer, and a fourth electrode. The drain is connected to a first signal. The gate is connected to a control signal to control the switch on or off. The source outputs the first signal when the switch turns on. The fourth electrode and the gate are respectively located at two sides of the semiconductor layer. The fourth electrode is conductive and is selectively coupled to different voltage levels, thereby reducing leakage current in a channel to improve switch characteristic when the switch turns off.

公开(公告)号：US09876099B2

公开(公告)日：2018-01-23

申请号：US15493215

申请日：2017-04-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masami Jintyou ,  Toshimitsu Obonai ,  Junichi Koezuka ,  Suzunosuke Hiraishi

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/786 ,  H01L21/441 ,  H01L21/4757 ,  H01L21/385

CPC classification number: H01L27/1225 ,  H01L21/385 ,  H01L21/441 ,  H01L21/47573 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: To suppress change in electric characteristics and improve reliability of a semiconductor device including a transistor formed using an oxide semiconductor. A semiconductor device includes a transistor including a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, and a pair of electrodes. The gate electrode and the oxide semiconductor film overlap with each other. The oxide semiconductor film is located between the first insulating film and the second insulating film and in contact with the pair of electrodes. The first insulating film is located between the gate electrode and the oxide semiconductor film. An etching rate of a region of at least one of the first insulating film and the second insulating film is higher than 8 nm/min when etching is performed using a hydrofluoric acid.

公开(公告)号：US09853069B2

公开(公告)日：2017-12-26

申请号：US15629970

申请日：2017-06-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi Suzawa ,  Shinya Sasagawa ,  Taiga Muraoka

IPC: H01L29/10 ,  H01L29/12 ,  H01L27/12 ,  H01L29/786 ,  H01L27/32 ,  G11C19/28 ,  G09G3/36 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/167 ,  G09F21/04

CPC classification number: H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

公开(公告)号：US20170352711A1

公开(公告)日：2017-12-07

申请号：US15120748

申请日：2016-06-27

Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd.

Inventor： Xiaoxing Zhang ,  Xingyu Zhou ,  Yuanjun Hsu

IPC: H01L27/32 ,  H01L51/00 ,  H01L51/52 ,  H01L51/56

CPC classification number: H01L27/3262 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/127

Abstract: The present invention provides a manufacture method of a TFT backplate and a TFT backplate. By utilizing the oxide semiconductor to manufacture the switch TFT, and utilizing the advantages of rapid switch and lower leakage current of the oxide semiconductor, the switch speed of the switch TFT is raised and the leakage current is lowered; by utilizing the polysilicon to manufacture the drive TFT, and utilizing the properties of higher electron mobility and the uniform grain of the polysilicon, the electron mobility and the current output consistency of the drive TFT is promoted. These are beneficial for the promotion of the light uniformity of the OLED element.

公开(公告)号：US20170352691A1

公开(公告)日：2017-12-07

申请号：US15175082

申请日：2016-06-07

Applicant: Eastman Kodak Company

Inventor： Carolyn Rae Ellinger

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L27/1262 ,  H01L21/0228 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/32 ,  H01L27/1218 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869

Abstract: A method device is prepared with a patterned thin film that can include one or more metal oxides on a suitable substrate. Initially, a pattern of a deposition inhibitor is provided on a surface of the substrate, which deposition inhibitor comprises at least one cellulose ester. This pattern has both inhibitor areas where the deposition inhibitor is present and open areas where the deposition inhibitor is absent. An inorganic thin film is then deposited on the surface of the substrate by a chemical vapor deposition process only in the open areas of the pattern. Further operations can be carried out including deposit of a second inorganic thin film exactly over the initial inorganic thin film, the deposition inhibitor can be removed from the inhibitor areas of the pattern, or both operations can be carried out in sequence.

公开(公告)号：US20170352534A1

公开(公告)日：2017-12-07

申请号：US15533718

申请日：2016-01-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei LIU

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/12

CPC classification number: H01L21/02304 ,  H01L21/02365 ,  H01L21/76841 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/127 ,  H01L27/1288 ,  H01L27/3262

Abstract: A method for manufacturing an array substrate comprises forming a pattern including an active layer, a gate insulating layer and a gate on a base substrate, and forming a pattern including an interlayer dielectric layer, a source, a drain and a pixel electrode through a single patterning process on the base substrate formed with the pattern of the active layer, the gate insulating layer and the gate. An array substrate and a display device are further provided.

公开(公告)号：US09837442B2

公开(公告)日：2017-12-05

申请号：US15246853

申请日：2016-08-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Junichiro Sakata ,  Masayuki Sakakura ,  Yoshiaki Oikawa ,  Kenichi Okazaki ,  Hotaka Maruyama ,  Masashi Tsubuku

IPC: G02F1/136 ,  H01L27/12 ,  H01L29/786 ,  G02F1/133 ,  G02F1/1345 ,  G02F1/1368 ,  G11C19/28 ,  H01L29/24 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1337 ,  G02F1/1339 ,  G02F1/1343 ,  G02F1/1362

CPC classification number: H01L27/1225 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/133528 ,  G02F1/1337 ,  G02F1/1339 ,  G02F1/13394 ,  G02F1/134336 ,  G02F1/13439 ,  G02F1/13454 ,  G02F1/136204 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/133357 ,  G02F2201/123 ,  G11C19/28 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/247 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696

Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is sandwiched between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected to each other in an opening provided in a gate insulating film through an oxide conductive layer.

公开(公告)号：US09825066B2

公开(公告)日：2017-11-21

申请号：US14990383

申请日：2016-01-07

Applicant: SAMSUNG DISPLAY CO., LTD

Inventor： Myung-Kwan Ryu ,  Eok-Su Kim ,  Kyoung Seok Son ,  Seung-Ha Choi ,  Sho-Yeon Kim ,  Hyun Kim ,  Eun-Hye Park ,  Byung-Hwan Chu

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L27/1248 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/41733 ,  H01L29/78696

Abstract: A thin film transistor substrate includes a gate electrode, a channel layer overlapping the gate electrode, a source electrode overlapping the channel layer, a drain electrode overlapping the channel layer and the source electrode, and a spacer disposed between the source electrode and the drain electrode.

公开(公告)号：US09825059B2

公开(公告)日：2017-11-21

申请号：US15334397

申请日：2016-10-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/786 ,  G02F1/133 ,  G02F1/1339 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/417 ,  H01L29/423 ,  G11C19/28 ,  G02F1/1333 ,  G02F1/1343 ,  G09G3/36

CPC classification number: H01L27/1225 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/1339 ,  G02F1/134309 ,  G02F1/136213 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2201/121 ,  G02F2201/123 ,  G09G3/3677 ,  G09G2310/0251 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28 ,  H01L27/088 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.

公开(公告)号：US20170330975A1

公开(公告)日：2017-11-16

申请号：US15531424

申请日：2015-11-19

Applicant: Sharp Kabushiki Kaisha

Inventor： HISAO OCHI ,  TOHRU DAITOH ,  HAJIME IMAI ,  TETSUO FUJITA ,  HIDEKI KITAGAWA ,  TETSUO KIKUCHI ,  MASAHIKO SUZUKI ,  SHINGO KAWASHIMA

IPC: H01L29/786 ,  C23C14/08 ,  H01L29/66 ,  H01L29/45 ,  H01L29/24 ,  H01L27/12 ,  H01L21/4763 ,  H01L21/441 ,  H01L21/02 ,  G02F1/1343 ,  G02F1/1368

CPC classification number: H01L29/78618 ,  C23C14/08 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2202/10 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/28 ,  H01L21/441 ,  H01L21/47635 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/24 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/50

Abstract: A semiconductor device (100A) includes a substrate (101) and a thin film transistor (10) supported by the substrate. The thin film transistor includes a gate electrode (102), an oxide semiconductor layer (104), a gate insulating layer (103), a source electrode (105) and a drain electrode (106). The oxide semiconductor layer includes an upper semiconductor layer (104b) which is in contact with the source electrode and the drain electrode and which has a first energy gap, and a lower semiconductor layer (104a) which is provided under the upper semiconductor layer and which has a second energy gap that is smaller than the first energy gap. The source electrode and the drain electrode include a lower layer electrode (105a, 106a) which is in contact with the oxide semiconductor layer and which does not contain Cu, and a major layer electrode (105b, 106b) which is provided over the lower layer electrode and which contains Cu. An edge of the lower layer electrode is at a position ahead of an edge of the major layer electrode.