公开(公告)号：US20170301673A1

公开(公告)日：2017-10-19

申请号：US15636055

申请日：2017-06-28

申请人： Texas Instruments Incorporated

发明人： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L27/088 ,  H01L29/10 ,  H01L29/417

CPC分类号： H01L27/092 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0883 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

摘要： An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

公开(公告)号：US09793416B2

公开(公告)日：2017-10-17

申请号：US15254529

申请日：2016-09-01

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Hidekazu Miyairi ,  Kengo Akimoto ,  Yasuo Nakamura

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L29/26 ,  H01L29/66 ,  H01L21/02 ,  H01L21/465 ,  H01L21/467 ,  H01L21/4763 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/10 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/78696 ,  H01L21/02323 ,  H01L21/02565 ,  H01L21/32139 ,  H01L21/465 ,  H01L21/467 ,  H01L21/4763 ,  H01L21/47635 ,  H01L27/1225 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/263 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78693

摘要： To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

公开(公告)号：US09793353B1

公开(公告)日：2017-10-17

申请号：US15464528

申请日：2017-03-21

申请人： Northrop Grumman Systems Corporation

发明人： Roger S. Tsai

IPC分类号： H01L29/786 ,  H01L29/15 ,  H01L29/417 ,  H01L29/06 ,  H01L29/778 ,  H03F3/193 ,  H01L29/78 ,  H01L27/088 ,  H01L29/205 ,  H03F1/32 ,  H01L21/8234

CPC分类号： H01L29/152 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0692 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/7783 ,  H01L29/785 ,  H01L29/78696 ,  H03F1/3205 ,  H03F3/193 ,  H03F2200/451 ,  H03F2201/3215

摘要： An exemplary FET includes a substrate and multiple vertically stacked layer groups with each layer group having a quantum well semiconductive layer and a nonconductive layer adjacent the first quantum well semiconductive layer. Conductive source and drain electrodes in conductive contact with the semiconductive layers. A 3-dimensional ridge of the stacked layer groups is defined between spaced apart first and second trenches which are between the source and drain electrodes. A continuous conductive side gate is disposed on the sides and top of the ridge for inducing a field into the semiconductive layers. A gate electrode is disposed in conductive contact with the conductive side gate.

公开(公告)号：US09786656B1

公开(公告)日：2017-10-10

申请号：US15241348

申请日：2016-08-19

申请人： International Business Machines Corporation

发明人： Brent A. Anderson ,  Xuefeng Liu ,  Junli Wang

IPC分类号： H01L21/8222 ,  H01L27/06 ,  H01L29/66 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/06 ,  H01L29/165 ,  H01L29/167 ,  H01L21/02 ,  H01L21/306 ,  H01L29/45 ,  H01L29/78 ,  H01L29/737

CPC分类号： H01L27/0623 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/8249 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/167 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66795 ,  H01L29/7371 ,  H01L29/7851

摘要： A fin heterojunction bipolar transistor (fin HBT) and a method of fabricating the fin HBT for integration with a fin complimentary metal-oxide-semiconductor (fin CMOS) into a BiCMOS fin device include forming a sub-collector layer on a substrate. The sub-collector layer includes silicon doped with arsenic (As+). A collector layer and base are patterned as fins along a first direction. An emitter layer is formed on the fins. The emitter layer is a continuous layer of epitaxially grown silicon. An oxide is deposited above the sub-collector layer, the base, and the emitter layer, and at least one contact is formed through the oxide to each of the sub-collector layer, the base, and the emitter layer.

公开(公告)号：US09786654B1

公开(公告)日：2017-10-10

申请号：US15298248

申请日：2016-10-20

申请人： UNITED MICROELECTRONICS CORP.

发明人： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC分类号： H01L23/62 ,  H01L27/02 ,  H01L29/06

CPC分类号： H01L27/0266 ,  H01L27/0262 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/87

摘要： An ESD protection semiconductor device includes a substrate, a first isolation structure disposed in the substrate, a gate disposed on the substrate and overlapping a portion of the first isolation structure, a source region formed in the substrate at a first side of the gate, and a drain region formed in the substrate at a second side of the gate opposite to the first side. The substrate and the drain region include a first conductivity type, the source region includes a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other.

公开(公告)号：US09780218B1

公开(公告)日：2017-10-03

申请号：US15144204

申请日：2016-05-02

申请人： UNITED MICROELECTRONICS CORPORATION

发明人： Sheng-Hsu Liu ,  Jhen-cyuan Li ,  Chih-Chung Chen ,  Man-Ling Lu ,  Chung-Min Tsai ,  Yi-wei Chen

IPC分类号： H01L31/072 ,  H01L31/109 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC分类号： H01L29/7851 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  Y02E10/50

摘要： A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

公开(公告)号：US09780089B2

公开(公告)日：2017-10-03

申请号：US15339779

申请日：2016-10-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Han-Min Tsai ,  Chi-Feng Huang ,  Chia-Chung Chen ,  Victor Chiang Liang ,  Hsiao-Chun Lee ,  Shou-Chun Chou ,  Shu-Fang Fu

IPC分类号： H01L29/66 ,  H01L27/082 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/735 ,  H01L27/02 ,  H01L29/417 ,  H01L29/423 ,  H01L23/00

CPC分类号： H01L27/082 ,  H01L23/562 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/735

摘要： A bipolar junction transistor includes an emitter, a base contact, a collector and a shallow trench isolation. The base contact has two base fingers that form a corner to receive the emitter. The collector has two collector fingers extending along the base fingers of the base contact. The shallow trench isolation is disposed in between the emitter and the base contact and in between the base contact and the collector.

公开(公告)号：US20170278923A1

公开(公告)日：2017-09-28

申请号：US15519701

申请日：2015-10-19

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Tatsuji NAGAOKA ,  Hiroki MIYAKE ,  Shinichiro MIYAHARA ,  Sachiko AOI

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L21/761 ,  H01L21/04 ,  H01L29/16 ,  H01L29/872

CPC分类号： H01L29/0623 ,  H01L21/0465 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： A technique stabilizing properties of SBDs is provided. An SBD is provided with a p-type contact region in contact with an anode electrode, and an n-type drift region in Schottky contact with the anode electrode. The p-type contact region includes a first p-type region having a corner portion, a second p-type region connected to the corner portion, and an edge filling portion located at a connection between the first p-type region and the second p-type region. First and second extended lines intersect at an acute angle, where the first extended line is a line extended from a contour of the first p-type region toward the connection and the second extended line is a line extended from a contour of the second p-type region toward the connection. An acute angle edge formed between the first extended line and the second extended line is filled with the edge filling portion.

公开(公告)号：US09773924B2

公开(公告)日：2017-09-26

申请号：US15089542

申请日：2016-04-02

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： Masao Uchida ,  Kouichi Saitou ,  Takayuki Wakayama

IPC分类号： H01L29/872 ,  H01L29/16 ,  H01L29/04 ,  H01L29/66 ,  H01L29/06 ,  H01L29/36 ,  H01L29/40

CPC分类号： H01L29/872 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/402 ,  H01L29/6606

摘要： A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface, wherein each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer, and each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to direction of crystal orientations of the semiconductor substrate.

公开(公告)号：US09773878B2

公开(公告)日：2017-09-26

申请号：US14793236

申请日：2015-07-07

申请人： FUJI ELECTRIC CO., LTD.

发明人： Takahide Tanaka ,  Masaharu Yamaji

IPC分类号： H01L29/40 ,  H01L29/739 ,  H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36

CPC分类号： H01L29/405 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4175 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7816 ,  H01L29/861

摘要： A semiconductor device includes a first main electrode terminal and second main electrode terminal disposed on the principal surface of a semiconductor substrate so as to be spaced from one another, an insulating film formed on the principal surface of the semiconductor substrate, and a thin film resistance layer. One end side of the thin film resistance layer is connected to the first main electrode terminal and the other end side of the thin film resistance layer is connected to the second main electrode terminal, the thin film resistance layer being spirally formed on the insulating film in such a way as to surround the first main electrode terminal. The thin film resistance layer extends while oscillating in a thickness direction of the semiconductor substrate.