公开(公告)号：US11853226B2

公开(公告)日：2023-12-26

申请号：US16624430

申请日：2018-05-15

Applicant: ARM LIMITED

Inventor： Andrew Brookfield Swaine

IPC: G06F12/00 ,  G06F12/1036 ,  G06F12/0864 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F12/0864 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/651 ,  G06F2212/657

Abstract: An apparatus has an address translation cache (12, 16) having a number of cache entries (40) for storing address translation data which depends on one or more page table entries of page tables. Control circuitry (50) is responsive to an invalidation request specifying address information to perform an invalidation lookup operation to identify at least one target cache entry to be invalidated. The target cache entry is an entry for which the corresponding address translation data depends on at least one target page table entry corresponding to the address information. The control circuitry (50) selects one of a number of invalidation lookup modes to use for the invalidation lookup operation in dependence on page size information indicating the page size of the target page table entry. The different invalidation lookup modes correspond to different ways of identifying the target cache entry based on the address information.

公开(公告)号：US20230370364A1

公开(公告)日：2023-11-16

申请号：US18361320

申请日：2023-07-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： David Charles Hewson ,  Timothy J. Johnson ,  Abdulla M. Bataineh

IPC: H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/00 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/00 ,  H04L69/40 ,  H04L47/10 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/16 ,  H04L45/021 ,  H04L47/12 ,  G06F13/42 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/62 ,  H04L47/24 ,  H04L49/90 ,  G06F13/38 ,  G06F13/40 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L45/12 ,  H04L47/122 ,  G06F12/1036 ,  G06F15/173 ,  H04L43/10 ,  H04L45/42 ,  H04L47/11 ,  G06F12/0862 ,  G06F12/1045 ,  H04L47/32 ,  G06F9/54 ,  G06F13/14 ,  G06F9/50 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  H04L47/762 ,  H04L47/78 ,  H04L47/20 ,  H04L49/9047 ,  H04L1/00 ,  H04L43/0876 ,  H04L47/2466 ,  H04L47/625

CPC classification number: H04L45/28 ,  G06F9/505 ,  G06F9/546 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1063 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/17331 ,  H04L1/0083 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/021 ,  H04L45/028 ,  H04L45/122 ,  H04L45/123 ,  H04L45/125 ,  H04L45/16 ,  H04L45/20 ,  H04L45/22 ,  H04L45/24 ,  H04L45/38 ,  H04L45/42 ,  H04L45/46 ,  H04L45/566 ,  H04L45/70 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/18 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/323 ,  H04L47/34 ,  H04L47/39 ,  H04L47/52 ,  H04L47/621 ,  H04L47/6235 ,  H04L47/626 ,  H04L47/6275 ,  H04L47/629 ,  H04L47/76 ,  H04L47/762 ,  H04L47/781 ,  H04L47/80 ,  H04L49/101 ,  H04L49/15 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9036 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  G06F2212/50 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L69/28

Abstract: Methods and systems are provided to facilitate network egress fairness between applications. At an egress port of a network, an arbitrator can provide fairness-based traffic shaping to data associated with applications. The desired fairness-based traffic shaping can be provided based on bandwidth, traffic classes, or other parameters. Consequently, the egress link’s bandwidth can be allocated with fairness among the applications.

公开(公告)号：US11768781B2

公开(公告)日：2023-09-26

申请号：US17827556

申请日：2022-05-27

Applicant: Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

Inventor： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

IPC: G06F9/455 ,  G06F9/50 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

CPC classification number: G06F13/16 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F13/4068 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/60 ,  G06F2212/68

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20230281133A1

公开(公告)日：2023-09-07

申请号：US17684231

申请日：2022-03-01

Applicant: Nuvia, Inc.

Inventor： Adrian MONTERO ,  Huzefa SANJELIWALA ,  Paul KITCHIN ,  Prarthna SANTHANAKRISHNAN ,  Conrado BLASCO ,  Pradeep KANAPATHIPILLAI

IPC: G06F12/1036 ,  G06F9/30 ,  G06F9/455

CPC classification number: G06F12/1036 ,  G06F9/30087 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/45558 ,  G06F2009/45562

Abstract: An electronic device includes one or more processors for executing one or more virtual machines. In response to a request for initiating a synchronization event, a processor identifies a subset of speculative memory access requests in one or more memory access request queues. Automatically and in accordance with the identifying, the processor purges translations associated with the subset of speculative memory access requests. Subsequent to the purging, the processor initiates the synchronization event. In some implementations, memory access completion is forced in response to a context synchronization event that corresponds to a termination of a first application, a termination of a first virtual machine, or a system call for updating a system register. Alternatively, in some implementations, memory access completion is forced in an operating system level or an application level in response to a data synchronization event that is initiated on a hypervisor layer or a firmware layer.

公开(公告)号：US11640361B2

公开(公告)日：2023-05-02

申请号：US16296306

申请日：2019-03-08

Applicant: International Business Machines Corporation

Inventor： Fadi Y. Busaba ,  Lisa Cranton Heller ,  Jonathan D. Bradbury

IPC: G06F12/14 ,  G06F12/109 ,  G06F12/1036 ,  G06F12/1072

Abstract: According to one or more embodiments of the present invention, a computer implemented method includes receiving a secure access request for a secure page of memory at a secure interface control of a computer system. The secure interface control can check a disable virtual address compare state associated with the secure page. The secure interface control can disable a virtual address check in accessing the secure page to support mapping of a plurality of virtual addresses to a same absolute address to the secure page based on the disable virtual address compare state being set and/or to support secure pages that are accessed using an absolute address and do not have an associated virtual address.

公开(公告)号：US20230042288A1

公开(公告)日：2023-02-09

申请号：US17867306

申请日：2022-07-18

Applicant: Intel Corporation

Inventor： Krystof C. Zmudzinski ,  Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Simon P. Johnson ,  Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Gilbert Neiger ,  Raghunandan Makaram ,  Carlos V. Rozas ,  Amy L. Santoni ,  Vincent R. Scarlata ,  Vedvyas Shanbhogue ,  Ilya Alexandrovich ,  Ittai Anati ,  Wesley H. Smith ,  Michael Goldsmith

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/14 ,  G06F9/455

Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

公开(公告)号：US20220350750A1

公开(公告)日：2022-11-03

申请号：US17242729

申请日：2021-04-28

Applicant: Arm Limited

Inventor： Charles Andrew GIEFER ,  Alexander Donald Charles CHADWICK

IPC: G06F12/1009 ,  G06F12/1036 ,  G06F12/02

Abstract: There is provided a data processing apparatus and method of data processing. The data processing apparatus comprises storage circuitry to store a hierarchy of page tables comprising an intermediate level page table. Each entry of the intermediate level page table comprises base address information of a next level page table and control information indicating whether an addressing function has been applied to reorder physical storage locations of entries of the next level page table. Address translation circuitry is provided to perform address translations in response to receipt of a virtual address by performing a lookup in a next level page table dependent on the base address information and a page table index from the virtual address. When the control information indicates that the addressing function has been applied, the lookup is performed at a modified storage location generated by applying the addressing function to the page table index.

公开(公告)号：US11467973B1

公开(公告)日：2022-10-11

申请号：US16146332

申请日：2018-09-28

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Sundeep Amirineni

IPC: G06F12/00 ,  G06F12/10 ,  G06F12/1018 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/1045 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1072

Abstract: Systems and methods are provided to perform fine-grained memory accesses using a memory controller. The memory controller can access elements stored in memory across multiple dimensions of a matrix. The memory controller can perform accesses to non-contiguous memory locations by skipping zero or more elements across any dimension of the matrix.

公开(公告)号：US11449437B2

公开(公告)日：2022-09-20

申请号：US16624494

申请日：2018-06-08

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Matthew Lucien Evans ,  Gareth Rhys Stockwell ,  Djordje Kovacevic

IPC: G06F12/14 ,  G06F21/60 ,  G06F12/1036 ,  G06F9/455

Abstract: An apparatus has processing circuitry for performing data processing in response to software processes and memory access circuitry for enforcing ownership rights for memory regions. A given memory region is associated with an owner realm specified from a multiple realms with each realm corresponding to a portion of at least one software process. The owner realm has a right to exclude other realms from accessing data stored in the given memory region (including realms executed at a higher privilege level). The realms are managed according to a realm hierarchy in which each realm other than a root realm is a child realm initialised in response to a command triggered by its parent realm. In response to an invalidation command, a realm management unit makes the target realm and any descendant realm of the target realm inaccessible to the processing circuitry.

公开(公告)号：US20220283954A1

公开(公告)日：2022-09-08

申请号：US17825977

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Aravinda Prasad ,  Sreenivas Subramoney

IPC: G06F12/1036

Abstract: Embodiments described herein are generally directed to maintaining contiguity of virtual to physical address mappings to exploit a contiguity-aware TLB. In an example, information regarding a migration set of one or more pages within a physical address space that have been identified for migration from a source tier of memory to a target tier of memory is received in which the physical address space comprises a first contiguous region of physical memory addresses and a VMA includes a second contiguous region of virtual memory addresses corresponding to the first contiguous region. It is determined whether the migration would break contiguity of a mapping maintained by a contiguity-aware TLB between pages of the first contiguous region and pages of the second contiguous region. Responsive an affirmative determination, discontinuities within the mapping resulting from the migration are minimized by intelligently increasing or decreasing the migration set.