Abstract:
A method to form an ultra-shallow junction is described. In one embodiment, a replacement gate process is utilized to enable the overlap of a gate electrode over the regions of a semiconductor substrate where tip extensions reside. In another embodiment, a sacrificial spacer is utilized in conjunction with the replacement gate process. In one embodiment, an initial gate electrode is formed with a gate length smaller than the desired final gate length and is subsequently replaced with an expanded gate electrode having the desired gate length.
Abstract:
In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.
Abstract:
A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.
Abstract:
A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
Abstract:
A method of forming a thin III-V semiconductor film on a semiconductor substrate, where the lattice structure of the III-V film is different than the lattice structure of the substrate. The method includes epitaxially growing the III-V film on the substrate until the III-V film is greater than 3.0 μm thick and then removing a portion of the III-V film until it is less than 3.0 μm thick. In one implementation, the III-V film is grown until it is around 8.0 μm to 10.0 μm thick, and then it is etched or polished until its thickness is reduced to 0.1 μm to 3.0 μm thick. By over-growing the III-V film, effects such as dislocation gliding and annihilation reduce the dislocation density of the film, thereby improving its electric mobility.
Abstract:
A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.
Abstract:
Embodiments of an apparatus and methods for providing a workfunction metal gate electrode on a substrate with doped metal oxide semiconductor structures are generally described herein. Other embodiments may be described and claimed.
Abstract:
At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
Abstract:
Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.
Abstract:
Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.