Forming ultra-shallow junctions
    101.
    发明授权
    Forming ultra-shallow junctions 有权
    形成超浅结

    公开(公告)号:US07456068B2

    公开(公告)日:2008-11-25

    申请号:US11449972

    申请日:2006-06-08

    Abstract: A method to form an ultra-shallow junction is described. In one embodiment, a replacement gate process is utilized to enable the overlap of a gate electrode over the regions of a semiconductor substrate where tip extensions reside. In another embodiment, a sacrificial spacer is utilized in conjunction with the replacement gate process. In one embodiment, an initial gate electrode is formed with a gate length smaller than the desired final gate length and is subsequently replaced with an expanded gate electrode having the desired gate length.

    Abstract translation: 描述了形成超浅结的方法。 在一个实施例中,利用替代栅极工艺来使栅电极在尖端延伸部分所在的半导体衬底的区域上重叠。 在另一个实施例中,牺牲间隔物与替代浇口工艺结合使用。 在一个实施例中,初始栅极形成的栅极长度小于期望的最终栅极长度,并且随后被具有期望栅极长度的扩展栅极电极替代。

    Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same
    103.
    发明授权
    Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same 有权
    具有隔离元件以减轻边缘效应的非平面微电子器件及其制造方法

    公开(公告)号:US07402856B2

    公开(公告)日:2008-07-22

    申请号:US11299102

    申请日:2005-12-09

    CPC classification number: H01L29/7851 H01L29/66795

    Abstract: A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.

    Abstract translation: 非平面微电子器件,制造器件的方法以及包括该器件的系统。 所述非平面微电子器件包括:衬底主体,其包括衬底基座和鳍片,所述鳍片限定其顶部区域处的器件部分; 栅极电介质层,其在所述鳍片的两个横向相对的侧壁上以预定高度延伸,所述预定高度对应于所述器件部分的高度; 在所述衬底主体上的器件隔离层,并且具有至所述器件部分的下限的厚度; 器件隔离层上的栅电极,并进一步在栅介质层上延伸; 隔离元件,其在所述鳍片的两个横向相对的侧壁上延伸到所述栅极电介质层的下限,所述隔离元件适于减小所述栅电极与所述鳍片延伸到所述器件部分下方的区域之间的任何条纹电容。

    Strain-inducing semiconductor regions
    104.
    发明申请
    Strain-inducing semiconductor regions 有权
    应变诱导半导体区域

    公开(公告)号:US20080142785A1

    公开(公告)日:2008-06-19

    申请号:US11450745

    申请日:2006-06-09

    Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

    Abstract translation: 描述形成应变诱导半导体区域的方法。 在一个实施方案中,形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变,从而提供应变的晶体衬底。 在另一个实施方案中,具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变,其中半导体区域的晶格常数与晶体衬底的晶格常数不同,以及 其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

    Thin III-V semiconductor films with high electron mobility
    105.
    发明申请
    Thin III-V semiconductor films with high electron mobility 审中-公开
    具有高电子迁移率的薄III-V半导体膜

    公开(公告)号:US20080132081A1

    公开(公告)日:2008-06-05

    申请号:US11633953

    申请日:2006-12-04

    Abstract: A method of forming a thin III-V semiconductor film on a semiconductor substrate, where the lattice structure of the III-V film is different than the lattice structure of the substrate. The method includes epitaxially growing the III-V film on the substrate until the III-V film is greater than 3.0 μm thick and then removing a portion of the III-V film until it is less than 3.0 μm thick. In one implementation, the III-V film is grown until it is around 8.0 μm to 10.0 μm thick, and then it is etched or polished until its thickness is reduced to 0.1 μm to 3.0 μm thick. By over-growing the III-V film, effects such as dislocation gliding and annihilation reduce the dislocation density of the film, thereby improving its electric mobility.

    Abstract translation: 在半导体衬底上形成薄的III-V半导体膜的方法,其中III-V膜的晶格结构不同于衬底的晶格结构。 该方法包括在衬底上外延生长III-V膜,直到III-V膜大于3.0μm厚,然后除去一部分III-V膜,直到其小于3.0μm厚。 在一个实施方案中,III-V膜生长直到其厚度约为8.0μm至10.0μm,然后进行蚀刻或抛光,直到其厚度减小至0.1μm至3.0μm厚。 通过过度生长III-V膜,如位错滑动和湮灭等作用降低了膜的位错密度,从而提高了其电迁移率。

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