公开(公告)号：US07456068B2

公开(公告)日：2008-11-25

申请号：US11449972

申请日：2006-06-08

Applicant: Jack T. Kavalieros ,  Mark Y. Liu ,  Suman Datta

Inventor： Jack T. Kavalieros ,  Mark Y. Liu ,  Suman Datta

IPC: H01L21/336 ,  H01L21/4763

CPC classification number: H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/7851

Abstract: A method to form an ultra-shallow junction is described. In one embodiment, a replacement gate process is utilized to enable the overlap of a gate electrode over the regions of a semiconductor substrate where tip extensions reside. In another embodiment, a sacrificial spacer is utilized in conjunction with the replacement gate process. In one embodiment, an initial gate electrode is formed with a gate length smaller than the desired final gate length and is subsequently replaced with an expanded gate electrode having the desired gate length.

Abstract translation: 描述了形成超浅结的方法。 在一个实施例中，利用替代栅极工艺来使栅电极在尖端延伸部分所在的半导体衬底的区域上重叠。 在另一个实施例中，牺牲间隔物与替代浇口工艺结合使用。 在一个实施例中，初始栅极形成的栅极长度小于期望的最终栅极长度，并且随后被具有期望栅极长度的扩展栅极电极替代。

公开(公告)号：US20080203381A1

公开(公告)日：2008-08-28

申请号：US11712191

申请日：2007-02-28

Applicant: Mantu K. Hudait ,  Jack T. Kavalieros ,  Suman Datta ,  Marko Radosavljevic

Inventor： Mantu K. Hudait ,  Jack T. Kavalieros ,  Suman Datta ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/151 ,  H01L29/201 ,  H01L29/207 ,  H01L29/365

Abstract: In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于形成逻辑器件的方法，包括在硅（Si）衬底上形成n型半导体器件，该衬底包括基于砷化铟镓（InGaAs）的堆叠，其包括第一缓冲层， 形成在第一缓冲层上的第二缓冲层，形成在第二缓冲层上的第一器件层。 此外，该方法可以包括从基于InGaAs的叠层在Si衬底上形成p型半导体器件，并且在n型半导体器件和p型半导体器件之间形成隔离。 描述和要求保护其他实施例。

公开(公告)号：US07402856B2

公开(公告)日：2008-07-22

申请号：US11299102

申请日：2005-12-09

Applicant: Justin K. Brask ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Robert S. Chau

Inventor： Justin K. Brask ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Robert S. Chau

IPC: H01L29/94

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.

Abstract translation: 非平面微电子器件，制造器件的方法以及包括该器件的系统。 所述非平面微电子器件包括：衬底主体，其包括衬底基座和鳍片，所述鳍片限定其顶部区域处的器件部分; 栅极电介质层，其在所述鳍片的两个横向相对的侧壁上以预定高度延伸，所述预定高度对应于所述器件部分的高度; 在所述衬底主体上的器件隔离层，并且具有至所述器件部分的下限的厚度; 器件隔离层上的栅电极，并进一步在栅介质层上延伸; 隔离元件，其在所述鳍片的两个横向相对的侧壁上延伸到所述栅极电介质层的下限，所述隔离元件适于减小所述栅电极与所述鳍片延伸到所述器件部分下方的区域之间的任何条纹电容。

公开(公告)号：US20080142785A1

公开(公告)日：2008-06-19

申请号：US11450745

申请日：2006-06-09

Applicant: Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

Inventor： Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

IPC: H01L31/00 ,  H01L29/06

CPC classification number: H01L29/1033 ,  H01L29/0673 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66787 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

Abstract translation: 描述形成应变诱导半导体区域的方法。 在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。 在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及 其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

公开(公告)号：US20080132081A1

公开(公告)日：2008-06-05

申请号：US11633953

申请日：2006-12-04

Applicant: Mohamad A. Shaheen ,  Mantu K. Hudait ,  Willy Rachmady ,  Jack T. Kavalieros ,  Chris E. Barns

Inventor： Mohamad A. Shaheen ,  Mantu K. Hudait ,  Willy Rachmady ,  Jack T. Kavalieros ,  Chris E. Barns

IPC: H01L21/00

CPC classification number: H01L21/0254 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02398 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549

Abstract: A method of forming a thin III-V semiconductor film on a semiconductor substrate, where the lattice structure of the III-V film is different than the lattice structure of the substrate. The method includes epitaxially growing the III-V film on the substrate until the III-V film is greater than 3.0 μm thick and then removing a portion of the III-V film until it is less than 3.0 μm thick. In one implementation, the III-V film is grown until it is around 8.0 μm to 10.0 μm thick, and then it is etched or polished until its thickness is reduced to 0.1 μm to 3.0 μm thick. By over-growing the III-V film, effects such as dislocation gliding and annihilation reduce the dislocation density of the film, thereby improving its electric mobility.

Abstract translation: 在半导体衬底上形成薄的III-V半导体膜的方法，其中III-V膜的晶格结构不同于衬底的晶格结构。 该方法包括在衬底上外延生长III-V膜，直到III-V膜大于3.0μm厚，然后除去一部分III-V膜，直到其小于3.0μm厚。 在一个实施方案中，III-V膜生长直到其厚度约为8.0μm至10.0μm，然后进行蚀刻或抛光，直到其厚度减小至0.1μm至3.0μm厚。 通过过度生长III-V膜，如位错滑动和湮灭等作用降低了膜的位错密度，从而提高了其电迁移率。

公开(公告)号：US07354832B2

公开(公告)日：2008-04-08

申请号：US11418295

申请日：2006-05-03

Applicant: Willy Rachmady ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Uday Shah

Inventor： Willy Rachmady ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Uday Shah

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.

Abstract translation: 一种制造三栅极半导体器件的方法，包括具有上表面和侧表面的半导体本体和在上表面和侧表面上具有大致相同厚度的金属栅极。 本文描述了具有保形物理气相沉积功能金属的三栅极器件在其三维体上的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20080073723A1

公开(公告)日：2008-03-27

申请号：US11525765

申请日：2006-09-22

Applicant: Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros ,  Brian S. Doyle

Inventor： Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros ,  Brian S. Doyle

IPC: H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/823842 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of an apparatus and methods for providing a workfunction metal gate electrode on a substrate with doped metal oxide semiconductor structures are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 在此通常描述用于在具有掺杂金属氧化物半导体结构的衬底上提供功函数金属栅电极的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US06953719B2

公开(公告)日：2005-10-11

申请号：US10851360

申请日：2004-05-20

Applicant: Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

Inventor： Mark Doczy ,  Justin K. Brask ,  Steven J. Keating ,  Chris E. Barns ,  Brian S. Doyle ,  Michael L. McSwiney ,  Jack T. Kavalieros ,  John P. Barnak

IPC: H01L21/3213 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66545 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7833 ,  Y10S438/926

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

公开(公告)号：US20200098887A1

公开(公告)日：2020-03-26

申请号：US16143326

申请日：2018-09-26

Applicant: Gilbert DEWEY ,  Van H. LE ,  Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Sean MA ,  Seung Hoon SUNG ,  Nazila HARATIPOUR ,  Tahir GHANI ,  Justin WEBER ,  Shriram SHIVARAMAN

Inventor： Gilbert DEWEY ,  Van H. LE ,  Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Sean MA ,  Seung Hoon SUNG ,  Nazila HARATIPOUR ,  Tahir GHANI ,  Justin WEBER ,  Shriram SHIVARAMAN

IPC: H01L29/51 ,  H01L29/786 ,  H01L29/49 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US09634007B2

公开(公告)日：2017-04-25

申请号：US14302350

申请日：2014-06-11

Applicant: Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L27/092 ,  H01L21/8258 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L21/845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.