公开(公告)号：US6057558A

公开(公告)日：2000-05-02

申请号：US34344

申请日：1998-03-04

Applicant: Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Kunihiko Hara ,  Yuichi Takeuchi ,  Kazukuni Hara ,  Masami Naito

Inventor： Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Kunihiko Hara ,  Yuichi Takeuchi ,  Kazukuni Hara ,  Masami Naito

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L31/0312

CPC classification number: H01L29/0847 ,  H01L29/0626 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7828 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238

Abstract: In a silicon carbide semiconductor device such as a trench gate type power MOSFET, the film thickness and the impurity concentration of a thin film silicon carbide semiconductor layer formed on a trench side face to constitute an accumulation-type channel-forming region and enable the device to operate with a low gate voltage, low on-resistance and low power loss are set so that on impression of a reverse bias voltage a pn junction between a P-type epitaxial layer and an n.sup.- -type epitaxial layer undergoes avalanche breakdown before the thin film silicon carbide semiconductor layer undergoes punch-through. By this means it is possible to obtain a target high source-drain withstand voltage.

Abstract translation: 在诸如沟槽栅型功率MOSFET的碳化硅半导体器件中，形成在沟槽侧面上的薄膜碳化硅半导体层的膜厚度和杂质浓度构成积聚型沟道形成区域，并使器件 以低栅极电压操作，设置低导通电阻和低功率损耗，使得在反向偏置电压的印象上，P型外延层和n型外延层之间的pn结在其之前经历雪崩击穿 薄膜碳化硅半导体层进行穿通。 通过这种方式，可以获得目标高的源极 - 漏极耐受电压。

公开(公告)号：US6054752A

公开(公告)日：2000-04-25

申请号：US107507

申请日：1998-06-30

Applicant: Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

Inventor： Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/34 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/0611 ,  H01L29/0638 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/1608

Abstract: A semiconductor device comprises a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer formed on the first semiconductor layer. A unit cell for controlling current flowing between a source electrode and a drain electrode is formed in the semiconductor substrate. A trench is formed in a peripheral region of the unit cell to form mesa structure. A field relaxing layer is formed between an insulating film on a side face of the second trench and both the first semiconductor layer and the second semiconductor layer in order to relax concentration of an electric field in the insulating film.

Abstract translation: 半导体器件包括：半导体衬底，包括形成在第一半导体层上的第一导电型第一半导体层和第二导电型第二半导体层。 在半导体衬底中形成用于控制在源电极和漏电极之间流动的电流的单元。 在单电池的周边区域形成沟槽，形成台面结构。 在第二沟槽的侧面上的绝缘膜与第一半导体层和第二半导体层之间形成场弛豫层，以使绝缘膜中的电场的集中化。

公开(公告)号：US5668985A

公开(公告)日：1997-09-16

申请号：US204992

申请日：1994-03-01

Applicant: Adrian L. Carbine ,  Gary L. Brown ,  Bradley D. Hoyt ,  Donald D. Parker ,  Rajesh Kumar

Inventor： Adrian L. Carbine ,  Gary L. Brown ,  Bradley D. Hoyt ,  Donald D. Parker ,  Rajesh Kumar

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30167 ,  G06F9/223 ,  G06F9/30145 ,  G06F9/3875

Abstract: A split queue system for a decoder that supplies one or more micro-operations and data associated with the micro-operations. A main queue is coupled to receive one or more micro-operations from the decoder, and supply it to a next processing stage to provide a process micro-operation. A shadow queue is coupled to receive data associated with the micro-operation, in the same cycle that the micro-operation is supplied to the main queue. A control circuit is coupled to the main queue for issuing micro-operation from the main queue into the next processing stage in a first cycle, and in a second cycle issuing, the micro-operation therefrom. Also in the second cycle, the control circuit issues the data associated with the micro-operation from the shadow queue, so that the data is synchronized with its associated processed micro-operation.

Abstract translation: 用于解码器的分离队列系统，其提供与微操作相关联的一个或多个微操作和数据。 主队列被耦合以从解码器接收一个或多个微操作，并将其提供给下一个处理阶段以提供处理微操作。 耦合影子队列以在微操作被提供给主队列的同一周期中接收与微操作相关联的数据。 控制电路耦合到主队列，用于在第一周期中从主队列发出微操作到下一个处理级，并且在第二周期中从其发出微操作。 同样在第二周期中，控制电路从影子队列发出与微操作相关联的数据，使得数据与其相关联的处理的微操作同步。

公开(公告)号：US20200056464A1

公开(公告)日：2020-02-20

申请号：US15999082

申请日：2018-08-17

Applicant: Leiming Li ,  Rajesh Kumar Saini

Inventor： Leiming Li ,  Rajesh Kumar Saini

IPC: E21B43/26 ,  C09K8/64 ,  C09K8/66 ,  C09K8/70 ,  C09K8/74

Abstract: A method for hydraulic fracturing of a subterranean formation includes injecting an oil-based fracturing fluid into the subterranean formation through a well. The method also includes injecting a second fracturing fluid, for example a water-based fracturing fluid, into the subterranean formation through the well after completion of the injection of the oil-based fracturing fluid.

公开(公告)号：US20190095789A1

公开(公告)日：2019-03-28

申请号：US15717690

申请日：2017-09-27

Applicant: Richard Stopic ,  Rajesh Kumar Aroli Veettil ,  Madhvesh Navkal Badri

Inventor： Richard Stopic ,  Rajesh Kumar Aroli Veettil ,  Madhvesh Navkal Badri

IPC: G06N3/08 ,  G06N5/02

Abstract: A method is disclosed. The method includes receiving, from a user computer that is a party to a transaction, information that can be used to identify a transaction between the user computer and a resource provider computer. The method further includes determining one or more attributes. The method additionally includes presenting a first question based on the one or more attributes. The method also includes receiving a response to the first question, presenting a second question based on the received response, and receiving a response to the second question. The method further includes storing the received responses in a data storage element, wherein the data storage element is accessible by an authorizing entity computer.

公开(公告)号：US10127558B2

公开(公告)日：2018-11-13

申请号：US12723371

申请日：2010-03-12

Applicant: Russell G. Bulman ,  Suresh Kumar ,  Sanket Karjagi ,  Ritwik Bose ,  Rajesh Kumar ,  Biswajit Nayak ,  Vikram Kamath ,  Bhavana Sumathi

Inventor： Russell G. Bulman ,  Suresh Kumar ,  Sanket Karjagi ,  Ritwik Bose ,  Rajesh Kumar ,  Biswajit Nayak ,  Vikram Kamath ,  Bhavana Sumathi

IPC: G06Q30/00 ,  G06Q40/00

Abstract: Systems and methods for automating an invoice approval process are described herein. Rules are created which are evaluated against a set of attributes. A rules engine is automatically invoked upon receipt of a document in an electronic invoice presentment and payment system. The rules engine determines which rules are applicable to documents received and processed in the system, and applies those applicable rules in a pre-defined sequence.

公开(公告)号：US09938454B2

公开(公告)日：2018-04-10

申请号：US14115395

申请日：2012-04-26

Applicant: Christopher Tanguay ,  Rajesh Kumar

Inventor： Christopher Tanguay ,  Rajesh Kumar

IPC: C09K8/80 ,  C02F1/00 ,  C02F1/28 ,  E21B43/267

CPC classification number: C09K8/805 ,  C02F1/001 ,  C02F1/288 ,  E21B43/267

Abstract: A proppant comprises a particle and a polymeric coating disposed about the particle. The polymeric coating comprises the reaction product of a novolac polyol, an isocyanate, and an azole. The novolac polyol has a number average molecular weight of from about 200 to about 1000 g/mol. A method of forming the proppant comprises the steps of providing the particle, providing the novolac polyol, providing the isocyanate, and providing the azole. The method also includes the steps of combining the novolac polyol, the isocyanate, and the azole to react and form the polymeric coating and coating the particle with the polymeric coating to form the proppant.

公开(公告)号：US20180009790A1

公开(公告)日：2018-01-11

申请号：US15532515

申请日：2015-12-24

Applicant: PRASAD RAJU VNKV VETUKURI ,  GOVERDHAN GILLA ,  RAJESH KUMAR RAPOLU ,  KRISHNA PRASAD CHIGURUPATI ,  GRANULES INDIA LIMITED

Inventor： PRASAD RAJU VNKV VETUKURI ,  GOVERDHAN GILLA ,  RAJESH KUMAR RAPOLU ,  KRISHNA PRASAD CHIGURUPATI

IPC: C07D403/14

CPC classification number: C07D403/14 ,  C07D403/04

Abstract: The present invention provides a novel process for the preparation of Ledipasvir of Formula I and its pharmaceutically acceptable salts.

公开(公告)号：US20170024001A1

公开(公告)日：2017-01-26

申请号：US15256006

申请日：2016-09-02

Applicant: HERBERT HUM ,  ERIC SPRANGLE ,  DOUG CARMEAN ,  RAJESH KUMAR

Inventor： HERBERT HUM ,  ERIC SPRANGLE ,  DOUG CARMEAN ,  RAJESH KUMAR

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract translation: 控制多个不对称核心之间的功率和处理的技术。 在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程。

公开(公告)号：US09519609B2

公开(公告)日：2016-12-13

申请号：US13995007

申请日：2011-12-22

Applicant: Thomas P. Thomas ,  Rajesh Kumar

Inventor： Thomas P. Thomas ,  Rajesh Kumar

IPC: G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4072 ,  G06F13/385 ,  G06F13/40 ,  G06F13/4086 ,  H01L2924/0002 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2924/00

Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

Abstract translation: 一个封装接口。 第一组第一组单端发射机电路。 发射机电路阻抗匹配，无均衡。 第二组芯片上的第一组单端接收器电路。 接收器电路没有终端，没有均衡。 多条导线耦合第一组发射机电路和第一组接收机电路。 多条导线的长度相匹配。