公开(公告)号：US06673710B1

公开(公告)日：2004-01-06

申请号：US09962754

申请日：2001-09-24

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2144

CPC classification number: H01L21/4853 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/1134 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K3/4046 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48

Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a conductive trace and an insulative base, wherein the chip includes a conductive pad and the insulative base contacts the conductive trace on a side opposite the chip, then forming a through-hole that extends through the insulative base and exposes the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract translation: 将导电迹线和绝缘基底连接到半导体芯片的方法包括提供半导体芯片，导电迹线和绝缘基底，其中所述芯片包括导电焊盘，并且所述绝缘基极在与所述芯片相对的一侧接触所述导电迹线 ，然后形成延伸穿过绝缘基底的通孔并暴露导电迹线和焊盘，然后形成接触和电连接导电迹线和焊盘的连接接头。

公开(公告)号：US06608374B1

公开(公告)日：2003-08-19

申请号：US10215944

申请日：2002-08-09

Applicant: Charles W. C. Lin ,  Cheng-Lien Chiang

Inventor： Charles W. C. Lin ,  Cheng-Lien Chiang

IPC: H01L2348

CPC classification number: H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/1134 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/4046 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05644

Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a base, wherein the chip includes a conductive pad, the base includes a recess, the conductive trace includes a bumped terminal in the recess, the bumped terminal includes a cavity that extends into and faces away from the recess, the base contacts and covers the conductive trace on a side opposite the chip, and the conductive trace and the base are different metals, mechanically attaching the chip to the conductive trace using an insulative adhesive that extends into the cavity, etching the base to expose the conductive trace, and forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the bumped terminal is inside a periphery of the chip, and the adhesive fills the cavity.

Abstract translation: 将导电迹线连接到半导体芯片的方法包括提供半导体芯片，导电迹线和基底，其中所述芯片包括导电焊盘，所述基底包括凹部，所述导电迹线包括在所述凹部中的凸起端子， 凸起端子包括延伸到凹部内并远离凹部的空腔，基部在与芯片相对的一侧上接触并覆盖导电迹线，并且导电迹线和基座是不同的金属，使用 延伸到空腔中的绝缘粘合剂，蚀刻基底以暴露导电迹线，以及形成接触和电连接导电迹线和焊盘的连接接头。 优选地，凸起端子在芯片的周边内，并且粘合剂填充空腔。

公开(公告)号：US06593224B1

公开(公告)日：2003-07-15

申请号：US10091683

申请日：2002-03-05

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L214763

CPC classification number: H05K3/4647 ,  H05K3/064 ,  H05K3/205 ,  H05K3/4652 ,  H05K3/4658 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2203/0733 ,  H05K2203/1476

Abstract: A method of manufacturing a multilayer interconnect substrate includes providing a first interconnect layer that includes a first conductive trace, wherein the first conductive trace includes a first pillar and a first routing line, and the first pillar protrudes vertically from and is electrically connected to the first routing line, providing a second interconnect layer that includes a second conductive trace, wherein the second conductive trace includes a second pillar and a second routing line, and the second pillar protrudes vertically from and is electrically connected to the second routing line, forming an opening in a dielectric layer between the first and second interconnect layers that exposes portions of the first pillar and the second routing line that were previously covered by the dielectric layer, and forming a connection joint in the opening that contacts and electrically connects the first pillar and the second routing line.

Abstract translation: 一种制造多层互连衬底的方法包括提供包括第一导电迹线的第一互连层，其中所述第一导电迹线包括第一柱和第一布线线，并且所述第一柱垂直地突出并且与所述第一导电迹线电连接 提供包括第二导电迹线的第二互连层，其中所述第二导电迹线包括第二支柱和第二路由线，并且所述第二支柱垂直地突出并与所述第二路由线电连接，形成开口 在第一和第二互连层之间的电介质层中，暴露出先前被介电层覆盖的第一柱和第二布线线的部分，并且在开口中形成接触和电连接第一柱和第二柱的连接接头 第二路由线路。

公开(公告)号：US06583040B1

公开(公告)日：2003-06-24

申请号：US10156277

申请日：2002-05-28

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2144

CPC classification number: H01L21/4853 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/1134 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K3/4046 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip and a laminated structure, wherein the chip includes a conductive pad, the laminated structure includes a conductive trace, an insulative base and a metal base, the conductive trace includes a routing line and a pillar, the metal base and the routing line are disposed on opposite sides of the insulative base, and the pillar contacts the routing line and extends through the insulative base and into the metal base, removing a portion of the metal base that contacts the pillar, and forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract translation: 制造半导体芯片组件的方法包括提供半导体芯片和层叠结构，其中所述芯片包括导电焊盘，所述层叠结构包括导电迹线，绝缘基底和金属基底，所述导电迹线包括布线线和 支柱，金属基座和布线线布置在绝缘基座的相对侧上，并且柱接触布线线并延伸穿过绝缘基底并进入金属基底，去除接触柱的金属基底的一部分 并且形成接触和电连接导电迹线和焊盘的连接接头。

公开(公告)号：US06576493B1

公开(公告)日：2003-06-10

申请号：US10188459

申请日：2002-07-03

Applicant: Charles W. C. Lin ,  Cheng-Lien Chiang

Inventor： Charles W. C. Lin ,  Cheng-Lien Chiang

IPC: H01L2144

CPC classification number: H01L23/5389 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/1134 ,  H01L2224/11474 ,  H01L2224/13008 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K3/4046 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip, a metal base, an insulative base and a conductive trace, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, and the conductive trace includes a contact terminal that extends through the insulative base, then forming an opening that extends through the metal base and the insulative base, exposes the pad and is spaced from the contact terminal, then forming a connection joint that contacts and electrically connects the conductive trace and the pad, and then removing a portion of the metal base that contacts the contact terminal. Preferably, the opening extends through an insulative adhesive that attaches the chip to the conductive trace.

Abstract translation: 制造半导体芯片组件的方法包括提供半导体芯片，金属基底，绝缘基底和导电迹线，其中芯片包括导电垫，金属基底设置在绝缘基底的远离 芯片和导电迹线包括延伸穿过绝缘基底的接触端子，然后形成延伸穿过金属基底和绝缘基底的开口，露出垫并与接触端子间隔开，然后形成连接接头， 接触并电连接导电迹线和焊盘，然后去除与接触端子接触的金属基体的一部分。 优选地，开口延伸穿过将芯片附接到导电迹线的绝缘粘合剂。

公开(公告)号：US06492252B1

公开(公告)日：2002-12-10

申请号：US09997973

申请日：2001-11-29

Applicant: Charles W. C. Lin ,  Cheng-Lien Chiang

Inventor： Charles W. C. Lin ,  Cheng-Lien Chiang

IPC: H01L2144

CPC classification number: H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/1134 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/4046 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05644

Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a base, wherein the chip includes a conductive pad, the base includes a recess, the conductive trace includes a bumped terminal in the recess, the bumped terminal includes a cavity that extends into and faces away from the recess, the base contacts and covers the conductive trace on a side opposite the chip, and the conductive trace and the base are different metals, mechanically attaching the chip to the conductive trace using an insulative adhesive that extends into the cavity, etching the base to expose the conductive trace, and forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the bumped terminal is inside a periphery of the chip, and the adhesive fills the cavity.

Abstract translation: 将导电迹线连接到半导体芯片的方法包括提供半导体芯片，导电迹线和基底，其中所述芯片包括导电焊盘，所述基底包括凹部，所述导电迹线包括在所述凹部中的凸起端子， 凸起端子包括延伸到凹部内并远离凹部的空腔，基部在与芯片相对的一侧上接触并覆盖导电迹线，并且导电迹线和基座是不同的金属，使用 延伸到空腔中的绝缘粘合剂，蚀刻基底以暴露导电迹线，以及形成接触和电连接导电迹线和焊盘的连接接头。 优选地，凸起端子在芯片的周边内，并且粘合剂填充空腔。

公开(公告)号：US06448644B1

公开(公告)日：2002-09-10

申请号：US09120408

申请日：1998-07-22

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2348

CPC classification number: H01L24/81 ,  H01L21/486 ,  H01L2224/11332 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A flip chip assembly, and methods of forming the same, including a single layer or multilayer substrate in which via holes serve as connections between a semiconductor chip and the substrate. The assembling steps comprise attaching an integrated circuit chip to a rigid or flexible dielectric substrate having a plurality of via holes for connecting respective traces on the substrate with respective input/output terminal pads of the integrated circuit chip. The via holes are aligned and placed on top of the pads so that the pads are totally or partially exposed through the opposite side of the substrate. Electrically conductive material is subsequently deposited in the via holes as well as on the surface of the pads to provide electrical connections between the integrated circuit chip and the traces of the dielectric circuitry. After the connections are made, the attachment between the chip and substrate can be removed or left as an integral part of the assembly since the connections also provide mechanical support. The contacting materials include electroless plated metals, electrochemical plated metals, solders, epoxies and conductive polymers.

Abstract translation: 倒装芯片组件及其形成方法，包括其中通孔用作半导体芯片和衬底之间的连接的单层或多层衬底。 组装步骤包括将集成电路芯片附接到具有多个通孔的刚性或柔性电介质基板，该通孔用于将基板上的各个迹线与集成电路芯片的相应输入/输出端子焊盘连接。 通孔对齐并放置在焊盘的顶部，使得焊盘完全或部分地暴露通过衬底的相对侧。 导电材料随后沉积在通孔以及焊盘的表面上，以提供集成电路芯片和电介质电路迹线之间的电连接。 在制造连接之后，芯片和基板之间的连接可以被移除或者作为组件的整体部分留下，因为连接也提供机械支撑。 接触材料包括无电镀金属，电化学电镀金属，焊料，环氧树脂和导电聚合物。

公开(公告)号：US06448108B1

公开(公告)日：2002-09-10

申请号：US09677207

申请日：2000-10-02

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2144

CPC classification number: H01L24/12 ,  H01L21/2885 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor chip assembly includes providing a semiconductor chip and a conductive metal, wherein the chip includes a conductive pad, the conductive metal includes a dimple, and the pad is aligned with the dimple, etching the conductive metal on a side opposite the dimple such that the dimple forms a through-hole in the conductive metal, and forming a connection joint in the through-hole that electrically connects the conductive metal and the pad. The method may include mechanically attaching the chip to the conductive metal using an adhesive before forming the through-hole, and forming an opening in the adhesive directly beneath the through-hole thereby exposing the pad after mechanically attaching the chip to the conductive metal and before forming the connection joint.

Abstract translation: 制造半导体芯片组件的方法包括提供半导体芯片和导电金属，其中所述芯片包括导电焊盘，所述导电金属包括凹坑，并且所述焊盘与所述凹坑对准，在相对的一侧蚀刻所述导电金属 所述凹坑使得所述凹坑在所述导电金属中形成通孔，并且在所述通孔中形成电连接所述导电金属和所述垫的连接接头。 该方法可以包括在形成通孔之前使用粘合剂机械地将芯片附接到导电金属，并且在通孔内直接在通孔下方形成开口，从而在将芯片机械地附接到导电金属之后并且在 形成连接接头。

公开(公告)号：US06350633B1

公开(公告)日：2002-02-26

申请号：US09643212

申请日：2000-08-22

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2144

CPC classification number: H01L24/12 ,  H01L21/2885 ,  H01L23/4985 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A semiconductor chip assembly includes a semiconductor chip attached to a support circuit. The support circuit includes an insulative base, a conductive trace and a through-hole between its top and bottom surfaces. The through-hole includes a top sidewall portion adjacent to the top surface and a bottom sidewall portion adjacent to the bottom surface. The conductive trace includes a pillar at the top surface and a routing line at the bottom sidewall portion. An electroplated contact terminal on the pillar extends above the base, and an electroplated connection joint in the through-hole contacts the routing line and the pad. Preferably, the connection joint is the only metal in the through-hole. A method of manufacturing the assembly includes simultaneously electroplating the contact terminal and the connection joint.

Abstract translation: 半导体芯片组件包括附接到支撑电路的半导体芯片。 支撑电路包括绝缘基座，导电迹线和在其顶表面和底表面之间的通孔。 通孔包括与顶表面相邻的顶侧壁部分和与底表面相邻的底侧壁部分。 导电迹线包括在顶表面处的柱和在底部侧壁部分处的路线。 柱上的电镀接触端子延伸到基座的上方，通孔中的电镀连接接头与布线线和焊盘接触。 优选地，连接接头是通孔中唯一的金属。 制造组件的方法包括同时电镀接触端子和连接接头。

公开(公告)号：US06350632B1

公开(公告)日：2002-02-26

申请号：US09665928

申请日：2000-09-20

Applicant: Charles W. C. Lin

Inventor： Charles W. C. Lin

IPC: H01L2148

CPC classification number: H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05144 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/78301 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05624 ,  H01L2224/05644

Abstract: A semiconductor chip assembly includes a semiconductor chip attached to a support circuit. The support circuit includes an insulative base, a conductive trace and a through-hole that extends through the conductive trace. A ball bond connection joint in the through-hole contacts and electrically connects the conductive trace and the pad. A method of manufacturing the assembly includes mechanically attaching the chip to the support circuit such that the through-hole exposes the pad, and then forming the ball bond in the through-hole using thermocompression or thermosonic wire bonding.

Abstract translation: 半导体芯片组件包括附接到支撑电路的半导体芯片。 支撑电路包括绝缘基底，导电迹线和延伸穿过导电迹线的通孔。 通孔中的球接头连接接头与导电迹线和焊盘电连接。 制造组件的方法包括将芯片机械地附接到支撑电路，使得通孔暴露焊盘，然后使用热压或热超声波引线键合在通孔中形成球接合。