公开(公告)号：US08304891B2

公开(公告)日：2012-11-06

申请号：US12315787

申请日：2008-12-04

申请人： Cheng-Chia Chiang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Jung-Pin Huang

发明人： Cheng-Chia Chiang ,  Chin-Huang Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Jung-Pin Huang

IPC分类号： H01L23/28 ,  H01L23/31 ,  H01L23/52 ,  H01L23/00

CPC分类号： H01L23/4334 ,  H01L21/486 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/81

摘要： A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.

摘要翻译： 提供了一种半导体封装器件，半导体封装结构及其制造方法，其主要包括在形成有TSV（透硅通孔）的晶片上设置多个半导体芯片，并将半导体芯片与TSV电连接; 用密封剂封装半导体芯片; 并将硬组分设置在密封剂上。 硬组件确保了在焊料凸块工艺期间晶片的平整度，并且在单独化处理期间提供对晶片的支撑，使得晶片可以牢固地位于单个载体上，从而克服现有技术的缺点，即难以安装焊料 碰撞，切割晶片难度大。

公开(公告)号：US07889511B2

公开(公告)日：2011-02-15

申请号：US12535397

申请日：2009-08-04

申请人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Wen-Tsung Tseng ,  Chih-Ming Huang

发明人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Wen-Tsung Tseng ,  Chih-Ming Huang

IPC分类号： H05K7/10

CPC分类号： H01R43/0256 ,  H01R43/0228 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

摘要： An electronic carrier board is provided, including a carrier, at least two paired bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings corresponding in position to the two bond pads. The openings are aligned in the same direction and expose at least a first sidewall and a second sidewall of each of the two bond pads. The first sidewall is perpendicular to an alignment direction of the bond pads and the second sidewall is parallel to the alignment direction of the bond pads. A distance between the first sidewall of at least one of the bond pads and a corresponding side of a corresponding one of the openings is at least about 50 μm greater than a distance between the second sidewall of the at least one bond pad and a corresponding side of the corresponding opening.

摘要翻译： 提供一种电子载体板，包括载体，形成在载体上的至少两个成对的接合焊盘和覆盖载体的保护层。 保护层形成有与两个接合焊盘相对应的开口。 开口沿相同方向排列，并暴露两个接合焊盘中的每一个的至少第一侧壁和第二侧壁。 第一侧壁垂直于接合焊盘的对准方向，第二侧壁平行于接合焊盘的对准方向。 至少一个接合焊盘的第一侧壁和对应的一个开口的对应侧之间的距离比至少一个接合焊盘的第二侧壁和相应的侧面之间的距离大至少约50μm 的相应开口。

公开(公告)号：US07679178B2

公开(公告)日：2010-03-16

申请号：US11974441

申请日：2007-10-12

申请人： Han-Ping Pu ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/02

CPC分类号： H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16151 ,  H01L2924/16195 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor package on which a semiconductor device can be stacked and fabrication method thereof are provided. The fabrication method includes the steps of mounting and electrically connecting at least one semiconductor chip on the substrate, mounting an electrical connecting structure consisting of an upper layer circuit board and a lower layer circuit board on the substrate and electrically connecting the electrical connecting structure to the substrate, where the semiconductor chip is received in a receiving space formed in the electrical connecting structure; forming an encapsulant on the substrate encapsulating the semiconductor chip and the electrical connecting structure, and after the encapsulant is formed, exposing top surface of the upper layer circuit board with a plurality of solder pads from the encapsulant to allow at least one semiconductor device to electrically connect the upper layer circuit board so as to form a stack structure.

摘要翻译： 提供半导体器件可堆叠的半导体封装件及其制造方法。 该制造方法包括以下步骤：在基板上安装和电连接至少一个半导体芯片，将由上层电路板和下层电路板组成的电连接结构安装在基板上，并将电连接结构电连接到 衬底，其中所述半导体芯片被容纳在形成在所述电连接结构中的接收空间中; 在封装半导体芯片和电连接结构的基板上形成密封剂，并且在形成密封剂之后，用来自密封剂的多个焊盘将上层电路板的顶表面曝光，以允许至少一个半导体器件电 连接上层电路板，形成堆叠结构。

公开(公告)号：US20090284850A1

公开(公告)日：2009-11-19

申请号：US12353726

申请日：2009-01-14

申请人： Chih-Ming Huang ,  Chih-Lun Chen

发明人： Chih-Ming Huang ,  Chih-Lun Chen

IPC分类号： G02B7/02

CPC分类号： G02B7/08

摘要： A device and a method for locking lens in a lens holder are provided, wherein the lens is configured in a voice-coil motor (VCM) of a camera module of a cell phone and the VCM has a lens holder for a lens being fixed inside. The device includes a circumgyration stop instrument having a bottom surface for urging against the top surface of the lens holder for preventing a lateral stress and a lateral movement from occurring on the lens holder while the circumgyration stopping unit is coupled with the lens holder.

摘要翻译： 提供一种用于将透镜锁定在透镜保持器中的装置和方法，其中透镜配置在手机的相机模块的音圈电机（VCM）中，并且VCM具有用于透镜的透镜保持器固定在内部 。 该装置包括一个环绕止动器具，其具有用于在镜片保持器与旋转镜架保持器联接的同时用于抵靠透镜保持器顶表面的底表面，用于防止横向应力和侧向运动发生在透镜保持器上。

公开(公告)号：US07573722B2

公开(公告)日：2009-08-11

申请号：US11654273

申请日：2007-01-16

申请人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Wen-Tsung Tseng ,  Chih-Ming Huang

发明人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Wen-Tsung Tseng ,  Chih-Ming Huang

IPC分类号： H05K7/10

CPC分类号： H01R43/0256 ,  H01R43/0228 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

摘要： An electronic carrier board is provided, including a carrier, at least two paired bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings corresponding in position to the two bond pads. The openings are aligned in the same direction and expose at least a first sidewall and a fourth sidewall of each of the two bond pads. The first sidewall and the fourth sidewall are both perpendicular to an alignment direction of the bond pads. A distance between the first sidewall of at least one of the bond pads and a corresponding side of a corresponding one of the openings is at least about 50 μm greater than a distance between the fourth sidewall of the at least one bond pad and a corresponding side of the corresponding opening.

摘要翻译： 提供一种电子载体板，包括载体，形成在载体上的至少两个成对的接合焊盘和覆盖载体的保护层。 保护层形成有与两个接合焊盘相对应的开口。 开口沿相同的方向排列，并暴露两个接合焊盘中的每一个的至少第一侧壁和第四侧壁。 第一侧壁和第四侧壁都垂直于接合焊盘的对准方向。 至少一个接合焊盘的第一侧壁与对应的一个开口的对应侧之间的距离比至少一个接合焊盘的第四侧壁与相应的侧面之间的距离大至少约50微米 的相应开口。

公开(公告)号：US20090004784A1

公开(公告)日：2009-01-01

申请号：US12204066

申请日：2008-09-04

申请人： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/56

CPC分类号： H01L21/4832 ,  H01L21/4857 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

摘要翻译： 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US07365364B2

公开(公告)日：2008-04-29

申请号：US11162135

申请日：2005-08-30

申请人： Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Yi Chang

发明人： Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Yi Chang

IPC分类号： H01L29/267 ,  H01L29/22

CPC分类号： H01L27/14683 ,  H01L27/14618 ,  H01L2224/24226

摘要： A sensor semiconductor device and a method for fabricating the same are proposed. A sensor chip is mounted on a substrate, and a dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the substrate and the sensor chip. The dielectric layer is formed with an opening for exposing a sensor region of the sensor chip. A light-penetrable lid covers the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip. The sensor chip can be electrically connected to an external device via a plurality of solder balls implanted on a surface of the substrate not for mounting the sensor chip. Therefore, the sensor semiconductor device is fabricated in a cost-effective manner, and circuit cracking and a know good die (KGD) problem are prevented.

摘要翻译： 提出了一种传感器半导体器件及其制造方法。 传感器芯片安装在基板上，并且在基板上形成电介质层和电路层，其中电路层电连接到基板和传感器芯片。 电介质层形成有用于暴露传感器芯片的传感器区域的开口。 透光盖子覆盖电介质层的开口，使得光线能够穿透透光盖子到达传感器区域并激活传感器芯片。 传感器芯片可以通过植入在基板的表面上的多个焊球电连接到外部设备，而不用于安装传感器芯片。 因此，传感器半导体器件以成本有效的方式制造，并且防止了电路破裂和知道的裸芯片（KGD）问题。

公开(公告)号：US07354796B2

公开(公告)日：2008-04-08

申请号：US11821269

申请日：2007-06-22

申请人： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/00

CPC分类号： H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/81801 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

摘要翻译： 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US07342318B2

公开(公告)日：2008-03-11

申请号：US11112145

申请日：2005-04-21

申请人： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L29/40

CPC分类号： H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/58 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K3/007 ,  H05K3/3457 ,  H05K3/4682 ,  H05K2203/0152 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

摘要翻译： 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US20070278701A1

公开(公告)日：2007-12-06

申请号：US11591800

申请日：2006-11-01

申请人： Cheng-Yi Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Chieh-Yuan Lin ,  Cheng-Hsu Hsiao

发明人： Cheng-Yi Chang ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Chieh-Yuan Lin ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/28

CPC分类号： H01L21/561 ,  H01L21/481 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a method for fabricating the same are disclosed. The method includes installing a plurality of conductive components on a plurality of chip carriers of a chip carrier module, connecting electrically the conductive components to electrical connection points of the adjacent chip carriers, mounting and electrically connecting a semiconductor chip to each of the chip carries, forming an encapsulant for enveloping the semiconductor chip and the conductive components, cutting the chip carriers to separate the conductive components installed thereon, exposing a portion of the conductive components out of the encapsulant, forming on the exposed portion of the conductive components an electroplated layer of nickel/gold, and separating the chip carriers from each other. The conductive components exposed out of the encapsulant provide extra electrical connection points and thereby promote the functionalities of electronic products.

摘要翻译： 公开了一种半导体封装及其制造方法。 该方法包括在芯片载体模块的多个芯片载体上安装多个导电组件，将导电组件电连接到相邻芯片载体的电连接点，将半导体芯片安装并电连接到每个芯片载体， 形成用于包封半导体芯片和导电部件的密封剂，切割芯片载体以分离安装在其上的导电组件，将一部分导电组分暴露于密封剂外，在导电组件的暴露部分上形成电镀层 镍/金，并且将芯片载体彼此分离。 从密封剂露出的导电组件提供额外的电连接点，从而促进电子产品的功能。