公开(公告)号：US06719884B2

公开(公告)日：2004-04-13

申请号：US10047308

申请日：2002-01-15

申请人： John Haig Marsh ,  Craig James Hamilton ,  Olek Peter Kowalski ,  Stuart Duncan McDougall ,  Xuefeng Liu ,  Bo-Cang Qui

发明人： John Haig Marsh ,  Craig James Hamilton ,  Olek Peter Kowalski ,  Stuart Duncan McDougall ,  Xuefeng Liu ,  Bo-Cang Qui

IPC分类号： C23C1434

CPC分类号： B82Y20/00 ,  H01L21/182 ,  H01S5/3413

摘要： A method of manufacturing an optical device, wherein the device body portion from which the device is to be made includes at least one Quantum Well, the method including the step of causing an impurity material including copper to intermix with the Quantum Well.

摘要翻译： 一种制造光学器件的方法，其中将要制造器件的器件主体部分包括至少一个量子阱，该方法包括使包括铜的杂质材料与量子阱混合的步骤。

公开(公告)号：US09310296B2

公开(公告)日：2016-04-12

申请号：US13164398

申请日：2011-06-20

申请人： Thaddeus G. Dziura ,  Yung-Ho Chuang ,  Bin-ming Benjamin Tsai ,  Xuefeng Liu ,  John J. Hench

发明人： Thaddeus G. Dziura ,  Yung-Ho Chuang ,  Bin-ming Benjamin Tsai ,  Xuefeng Liu ,  John J. Hench

IPC分类号： G05B13/00 ,  G01N21/47 ,  G01B11/24 ,  G03F7/20 ,  G01N21/956 ,  G06F17/50

CPC分类号： G01B11/24 ,  G01B2210/56 ,  G01N21/47 ,  G01N21/956 ,  G01N2021/95615 ,  G03F7/70625 ,  G06F17/5009

摘要： Optimization of optical parametric models for structural analysis using optical critical dimension metrology is described. A method includes determining a first optical model fit for a parameter of a structure. The first optical model fit is based on a domain of quantities for a first model of the structure. A first near optical field response is determined for a first quantity of the domain of quantities and a second near optical field response is determined for a second, different quantity of the domain of quantities. The first and second near optical field responses are compared to locate a common region of high optical field intensity for the parameter of the structure. The first model of the structure is modified to provide a second, different model of the structure. A second, different optical model fit is determined for the parameter of the structure based on the second model of the structure.

摘要翻译： 描述了使用光学关键尺寸度量结构分析的光学参数模型的优化。 一种方法包括确定适合结构参数的第一光学模型。 第一个光学模型拟合是基于结构的第一个模型的数量域。 对于第一量的量域确定第一近场光响应，并且针对量的第二个不同数量的量确定第二近场光响应。 比较第一和第二近场光响应，以定位用于结构参数的高光场强度的公共区域。 该结构的第一个模型被修改以提供第二个不同的结构模型。 基于结构的第二个模型，确定结构参数的第二个不同的光学模型拟合。

公开(公告)号：US08592293B2

公开(公告)日：2013-11-26

申请号：US13028673

申请日：2011-02-16

申请人： Jeffrey B. Johnson ,  Xuefeng Liu ,  Bradley A. Orner ,  Robert M. Rassel

发明人： Jeffrey B. Johnson ,  Xuefeng Liu ,  Bradley A. Orner ,  Robert M. Rassel

IPC分类号： H01L21/28

CPC分类号： H01L29/872 ,  H01L21/8249 ,  H01L27/0635 ,  H01L27/0814 ,  H01L29/161 ,  H01L29/47 ,  H01L29/66143

摘要： A method for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.

摘要翻译： 一种在SiGe BiCMOS晶片上形成肖特基势垒二极管的方法，包括形成提供高于约1.0THz的截止频率（Fc）的结构。 在实施例中，提供高于约1.0THz的截止频率（Fc）的结构可以包括具有提供高于约1.0THz的截止频率（FC）的阳极区域的阳极，具有提供截止频率 频率（FC）高于约1.0THz，在提供高于约1.0THz的截止频率（FC）的能量和剂量下的p型防护，所述p型护罩具有提供高于约截止频率（FC）的尺寸 1.0 THz，以及具有n型掺杂剂的良好裁缝，其提供高于约1.0THz的截止频率（FC）。

公开(公告)号：US20130187198A1

公开(公告)日：2013-07-25

申请号：US13358180

申请日：2012-01-25

申请人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

发明人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

IPC分类号： H01L29/737 ,  G06F17/50 ,  H01L21/331

CPC分类号： H01L29/417 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371

摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.

摘要翻译： 提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。 收集器触点有利地延伸穿过外部基极层的至少一部分。

公开(公告)号：US08421183B2

公开(公告)日：2013-04-16

申请号：US13016126

申请日：2011-01-28

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L23/552 ,  H01L21/76 ,  H01L21/76264 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

公开(公告)号：US20130080984A1

公开(公告)日：2013-03-28

申请号：US13411433

申请日：2012-03-02

申请人： Xuefeng Liu ,  Yung-Ho Alex Chuang ,  John Fielden ,  Bin-Ming Benjamin Tsai ,  Jingjing Zhang

发明人： Xuefeng Liu ,  Yung-Ho Alex Chuang ,  John Fielden ,  Bin-Ming Benjamin Tsai ,  Jingjing Zhang

IPC分类号： G06F17/50

CPC分类号： G06F17/5018 ,  G03F7/70625 ,  G06F17/10 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G06F2217/16 ,  H01L22/12 ,  H01L22/20

摘要： Systems and methods for process aware metrology are provided.

摘要翻译： 提供了流程感知度量的系统和方法。

公开(公告)号：US08338920B2

公开(公告)日：2012-12-25

申请号：US11690682

申请日：2007-05-08

申请人： John Michael Cotte ,  Hanyi Ding ,  Kai Di Feng ,  Zhong-Xiang He ,  Nils D. Hoivik ,  Xuefeng Liu

发明人： John Michael Cotte ,  Hanyi Ding ,  Kai Di Feng ,  Zhong-Xiang He ,  Nils D. Hoivik ,  Xuefeng Liu

IPC分类号： H01L23/552

CPC分类号： H01L23/04 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/645 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01042

摘要： An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.

摘要翻译： 集成电路封装包括具有一个或多个片上电感器的集成电路。 封装盖覆盖集成电路。 磁性材料设置在集成电路和封装盖之间。 磁性材料可以是软磁性薄膜。 磁性材料可以通过粘合剂固定到包装盖上。 磁性材料可以通过沉积，溅射或喷涂之一直接形成在封装盖上。 磁性材料可以固定在集成电路上。

公开(公告)号：US20120266116A1

公开(公告)日：2012-10-18

申请号：US13534350

申请日：2012-06-27

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

IPC分类号： G06F17/50

CPC分类号： H01Q1/2283 ,  H01Q1/40 ,  H01Q9/26 ,  H01Q9/285 ,  H01Q19/108 ,  H01Q19/30

摘要： A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.

摘要翻译： 提供集成收发器，天线和接收器的半导体芯片。 收发器位于半导体衬底的前侧。 通过基底通孔提供收发器和位于半导体衬底背面的接收器之间的电连接。 连接到收发器的天线位于位于基板正面的电介质层中。 反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。 可以采用贯穿衬底电介质通孔的阵列来降低天线和反射板之间材料的有效介电常数，由此减小毫米波的波长并提高辐射效率。 还提供了用于设计，制造或测试这种半导体芯片的设计的设计结构。

公开(公告)号：US08279572B2

公开(公告)日：2012-10-02

申请号：US12144095

申请日：2008-06-23

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

IPC分类号： H02H9/02

CPC分类号： H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.

摘要翻译： 描述了片上高频静电放电装置的设计结构。 在一个实施例中，静电放电结构包括其中形成有多于一个电极的第一电介质层。 其中形成有多于一个电极的第二电介质层位于第一介电层的上方。 至少一个通孔将第一介电层中的多于一个的电极与第二介电层中的多于一个的电极连接。 通过第一电介质层和第二电介质层形成间隙，其中间隙在第一电介质层和第二电介质层中的两个相邻电极之间延伸。 第三电介质层设置在第二电介质层上，其中第三介电层气密地密封间隙以在集成电路上提供静电放电保护。

公开(公告)号：US08138579B2

公开(公告)日：2012-03-20

申请号：US11867995

申请日：2007-10-05

申请人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

发明人： Xuefeng Liu ,  Robert M. Rassel ,  Steven H. Voldman

IPC分类号： H01L23/58

CPC分类号： H01L29/165 ,  H01L21/84 ,  H01L27/0652 ,  H01L27/1203

摘要： Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions. The invention is also directed to a design structure on which a circuit resides.

摘要翻译： 半导体结构和形成半导体结构的方法，更具体地涉及用于形成用于SOI / SiGe器件的SiGe和/或SiGeC掩埋层的结构和方法。 集成结构包括具有交替的Si和SiGe或SiGeC区域的不连续的掩埋层。 该结构还包括在Si和SiGe或SiGeC区域之间的界面处的隔离结构，以减少交替区域之间的缺陷。 器件与Si和SiGe或SiGeC区域相关联。 本发明还涉及电路所在的设计结构。