公开(公告)号：US20200335401A1

公开(公告)日：2020-10-22

申请号：US16390226

申请日：2019-04-22

申请人： International Business Machines Corporation

发明人： Su Chen Fan ,  Ruilong Xie ,  Veeraraghavan S. Basker ,  Andre P. Labonte ,  Chanro Park

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78

摘要： Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes forming a first transistor and a second transistor over a substrate. The first transistor includes a first gate structure having a first gate spacer, and the second transistor includes a second gate structure having a second gate spacer. A top portion of the first gate spacer is replaced with a first sacrificial gate spacer region, and a top portion of the second gate spacer is replaced with a second sacrificial gate spacer region. A source or drain (S/D) conductive plug trench and a S/D cap trench are formed in the dielectric region of the IC and positioned over a S/D region of the first transistor. A volume of the S/D cap trench is increased by removing the first sacrificial gate spacer region and/or the second sacrificial gate spacer region.

公开(公告)号：US20200328088A1

公开(公告)日：2020-10-15

申请号：US16378844

申请日：2019-04-09

申请人： International Business Machines Corporation

发明人： Juntao Li ,  Kangguo Cheng ,  Ruilong Xie ,  Chanro Park

IPC分类号： H01L21/311 ,  H01L29/423 ,  H01L27/092 ,  H01L21/033 ,  H01L21/3205 ,  G01N27/414

摘要： A semiconductor device includes a first passivation layer disposed on a semiconductor base. The semiconductor device further includes a dielectric layer disposed on the first passivation layer. The semiconductor device further includes a plurality of pillars disposed in an opening in the dielectric layer and the first passivation layer and from a top surface of the semiconductor base. The semiconductor device further includes a metal layer disposed on the exterior surfaces of the plurality of pillars and sidewalls of the dielectric layer and the first passivation layer and on the exposed top surface of the semiconductor base. The semiconductor device further includes a second passivation layer disposed on the metal layer and a top surface of the semiconductor device; wherein the second passivation layer has an electrical charge.

公开(公告)号：US10790395B2

公开(公告)日：2020-09-29

申请号：US16006377

申请日：2018-06-12

申请人： International Business Machines Corporation

发明人： Injo Ok ,  Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065

摘要： A semiconductor device is described. The semiconductor device includes a dielectric layer oriented substantially parallelly to a substrate. The semiconductor device includes a metal layer formed on top of the dielectric layer. The semiconductor device includes a fin extending substantially orthogonally from the substrate through the dielectric layer into the metal layer. The semiconductor device includes a gate insulator deposited on top of the fins and the dielectric layer. The semiconductor device includes an optical projection lithography (OPL) material deposited on a portion of a surface area of the device to form a first covered surface area and a first exposed surface area. The semiconductor device includes a first exposed gate insulator area formed by removing the metal layer under the first exposed surface area. The semiconductor device includes a first exposed fin area formed by removing the gate insulator from the first exposed gate insulator area. The semiconductor device includes a substantially planar self-aligning gate cap filling a recess in the first exposed fin area and an adjacent area of the metal layer.

公开(公告)号：US10770562B1

公开(公告)日：2020-09-08

申请号：US16290182

申请日：2019-03-01

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Juntao Li ,  Andrew Greene ,  Vimal Kamineni ,  Adra Carr ,  Chanro Park ,  Ruilong Xie

IPC分类号： H01L21/00 ,  H01L29/45 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3105 ,  H01L21/321 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/762

摘要： Techniques are provided for fabricating a semiconductor integrated circuit device which implement an interlayer dielectric (ILD) layer replacement process to replace an initial sacrificial ILD layer with a low-k ILD layer, while forming silicide or dielectric capping layers to protect source/drain contacts of field-effect transistor devices from etch damage during the ILD replacement process. For example, source/drain contact openings (e.g., trenches) are formed in a sacrificial ILD layer and metallic source/drain contacts are formed in the source/drain contact openings. Protective capping layers (e.g., metal-semiconductor alloy capping layers or dielectric capping layers) are formed on upper surfaces of the metallic source/drain contacts. The sacrificial ILD layer is removed using an etch process to etch down the sacrificial ILD layer selective to the protective capping layers, and a low-k ILD layer is formed in place of the removed sacrificial ILD layer.

公开(公告)号：US10746691B1

公开(公告)日：2020-08-18

申请号：US16281183

申请日：2019-02-21

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Chanro Park ,  Ruilong Xie ,  Juntao Li

IPC分类号： G01N27/414

摘要： An ion-sensitive field effect transistor (ISFET) is provided that has enhanced sensitivity due to an increased passivation capacitance, Cp. The increased Cp is obtained by increasing the surface area of the passivation layer by forming particles (metallic, semiconductor or dielectric) in a micro-well, and by embedding the particles in an electrically conductive liner that is formed under the passivation layer and within the micro-well.

公开(公告)号：US20180047615A1

公开(公告)日：2018-02-15

申请号：US15232341

申请日：2016-08-09

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Thomas J. Haigh ,  Juntao Li ,  Eric G. Liniger ,  Sanjay C. Mehta ,  Son V. Nguyen ,  Chanro Park ,  Tenko Yamashita

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76852 ,  H01L23/528 ,  H01L23/5329 ,  H01L29/41775 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

摘要： Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

公开(公告)号：US09583584B2

公开(公告)日：2017-02-28

申请号：US14795984

申请日：2015-07-10

申请人： GLOBALFOUNDRIES, INC. ,  International Business Machines Corporation

发明人： Chanro Park ,  Injo Ok

IPC分类号： H01L21/70 ,  H01L29/49 ,  H01L29/66 ,  H01L21/82

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/70 ,  H01L21/82 ,  H01L21/82345 ,  H01L21/823456 ,  H01L29/66545

摘要： Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.

摘要翻译： 提供了集成电路及其制造方法。 在示例性实施例中，用于制造集成电路的方法包括形成覆盖在基板和多个电介质柱上的功函数层。 电介质柱和衬底限定具有短区域宽度的短区域和具有大于短区域宽度的长区域宽度的长区域。 工作功能层在长区域中凹陷到介电柱顶表面和基板顶表面之间的长区域功函数高度。 工作功能层也在短区域中凹陷到介电柱顶表面和衬底顶表面之间的短区域功函数高度。 在没有光刻技术的情况下，在长和短区域内嵌入功函数层。

公开(公告)号：US20240357822A1

公开(公告)日：2024-10-24

申请号：US18305653

申请日：2023-04-24

申请人： International Business Machines Corporation

发明人： Min Gyu Sung ,  Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Juntao Li

IPC分类号： H10B43/35 ,  H01L23/528 ,  H01L25/065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B80/00

CPC分类号： H10B43/35 ,  H01L23/5283 ,  H01L25/0657 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B80/00

摘要： A memory device including a stack of nanostructures, a first plurality of nanosheets/nanowires from the stack of nanostructures having first source and drain regions at their opposing ends to position first channel regions for a first memory cell, and a second plurality of nanosheets/nanowires from the stack of nanostructures having second source and drain regions at their opposing ends to position second channel regions for a second memory cell. An isolation liner layer is present between the first source and drain regions and the second source and drain regions. The memory device further includes a shared gate all around (GAA) control gate for the first and second memory cell, the shared gate all around (GAA) control gate including tunnel dielectric layer on the first and second channel regions, a trap dielectric layer on the tunnel dielectric layer, and a control conductor on the trap dielectric layer.

公开(公告)号：US20240332182A1

公开(公告)日：2024-10-03

申请号：US18129048

申请日：2023-03-30

申请人： International Business Machines Corporation

发明人： Yann Mignot ,  Shahab Siddiqui ,  Chanro Park ,  Ruilong Xie

IPC分类号： H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

摘要： A MOSFET includes a semiconductor substrate that has a frontside and a backside; a metal gate at the frontside of the substrate; a first source/drain structure at the frontside of the substrate, adjacent to the metal gate in a first direction; and a first source/drain contact at the frontside of the first source/drain structure. Also included are a backside power rail at the backside of the substrate; and a recessed via that connects the first source/drain contact through the substrate to the backside power rail. The recessed via is adjacent to the first source/drain structure in a direction perpendicular to the first direction. A dielectric cap covers a frontside of the first source/drain contact. A gate contact is disposed at a frontside of the dielectric cap. The gate contact at least partly overlies the first source/drain contact.

公开(公告)号：US12107014B2

公开(公告)日：2024-10-01

申请号：US17490266

申请日：2021-09-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Julien Frougier ,  Huimei Zhou ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

IPC分类号： H01L29/775 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0924 ,  H01L29/66545

摘要： Semiconductor devices and methods of forming the same include a first device region, a second device region, and an inter-device dielectric spacer between the first device region and the second device region. The first device region includes a first device channel, a first-polarity work function metal layer on the first device channel, and a second-polarity work function metal layer on the first device channel. The second device region include a second device channel, and a second-polarity work function metal layer on the second device channel.