公开(公告)号：US20200210077A1

公开(公告)日：2020-07-02

申请号：US16235407

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Naveh Malihi

IPC: G06F3/06

Abstract: Apparatuses and methods related to implementing a non-persistent unlock state for secure memory. Implementing the non-persistent unlock state can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated following the placement of the protected region in a non-persistent unlocked mode. If the row of the memory array corresponding to the access command is activated, then the protected region can be placed on a locked mode.

公开(公告)号：US10699784B2

公开(公告)日：2020-06-30

申请号：US16057170

申请日：2018-08-07

Applicant: Micron Technology, Inc.

Inventor： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

IPC: G11C13/00 ,  G11C11/16

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

公开(公告)号：US10468382B2

公开(公告)日：2019-11-05

申请号：US15137931

申请日：2016-04-25

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

IPC: B23P19/00 ,  H01L25/065 ,  H01L23/50 ,  H01L23/66 ,  H01L23/538

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

公开(公告)号：US20190122950A1

公开(公告)日：2019-04-25

申请号：US16229257

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L23/367 ,  H01L25/00 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US10157926B2

公开(公告)日：2018-12-18

申请号：US15664161

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  H01L29/78 ,  G11C11/403 ,  H01L23/528 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US20180190367A1

公开(公告)日：2018-07-05

申请号：US15910889

申请日：2018-03-02

Applicant: Micron Technology, Inc.

Inventor： Joe M. Jeddeloh ,  Brent Keeth

IPC: G11C29/44 ,  G06F11/10 ,  G06F11/16 ,  G11C29/00 ,  G06F11/07 ,  G06F11/20 ,  G11C29/04

CPC classification number: G11C29/4401 ,  G06F11/073 ,  G06F11/1072 ,  G06F11/1088 ,  G06F11/1666 ,  G06F11/2017 ,  G11C29/702 ,  G11C29/785 ,  G11C29/789 ,  G11C2029/0401 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.

公开(公告)号：US10002659B2

公开(公告)日：2018-06-19

申请号：US15265677

申请日：2016-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

IPC: G06F13/10 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

公开(公告)号：US20170352388A1

公开(公告)日：2017-12-07

申请号：US15620490

申请日：2017-06-12

Applicant: Micron Technology, Inc.

Inventor： Joe M. Jeddeloh ,  Brent Keeth

IPC: G11C5/06 ,  G11C7/10 ,  G11C5/02 ,  H01L25/065 ,  G11C5/14 ,  G11C11/4063

CPC classification number: G11C5/066 ,  G11C5/025 ,  G11C5/14 ,  G11C7/10 ,  G11C11/4063 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

公开(公告)号：US09697883B2

公开(公告)日：2017-07-04

申请号：US15052161

申请日：2016-02-24

Applicant: Micron Technology, Inc.

Inventor： Jacob Baker ,  Brent Keeth

IPC: H04B10/00 ,  G11C11/4093 ,  G06F13/16 ,  G11C11/42 ,  G06F13/28 ,  G06F13/42 ,  H04B10/80 ,  H04L12/40 ,  H04Q11/00

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/287 ,  G06F13/4234 ,  G11C11/42 ,  H04B10/802 ,  H04L12/40013 ,  H04Q11/0071 ,  Y02D10/14 ,  Y02D10/151

Abstract: A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.

公开(公告)号：US09484326B2

公开(公告)日：2016-11-01

申请号：US14563222

申请日：2014-12-08

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Christopher K. Morzano

IPC: G06F13/14 ,  H01L25/065 ,  G06F13/38 ,  H01L23/48 ,  H01L25/18 ,  G11C5/02 ,  H01L23/31

CPC classification number: H01L25/0652 ,  G06F13/385 ,  G11C5/02 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555

Abstract: Various embodiments include apparatuses having stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.

Abstract translation: 各种实施例包括具有堆叠装置的装置和在接口管芯上形成管芯叠层的方法。 在一种这样的装置中，骰子堆叠包括至少第一模具和第二模具，以及将第一模具和第二模具耦合到公共控制模具的导电路径。 在一些实施例中，导电路径可以布置成与堆叠的交替管芯上的电路连接。 在其他实施例中，多个骰子堆可以被布置在单个接口管芯上，并且骰子的一些或全部可以具有交错导电路径。