公开(公告)号：US11818968B2

公开(公告)日：2023-11-14

申请号：US17410591

申请日：2021-08-24

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Tao D. Nguyen ,  John Mark Meldrim ,  Aaron K. Belsher

IPC: G11C5/06 ,  H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/823 ,  G11C13/004 ,  G11C13/0028 ,  H10B63/80 ,  H10N70/061 ,  H10N70/882 ,  H10N70/231

Abstract: Some embodiments include an integrated assembly having an insulative mass over a conductive base structure. A conductive interconnect extends through the insulative mass to an upper surface of the conductive base structure. The conductive interconnect includes a conductive liner extending around an outer lateral periphery of the interconnect. The conductive liner includes nitrogen in combination with a first metal. A container-shaped conductive structure is laterally surrounded by the conductive liner. The container-shaped conductive structure includes a second metal. A conductive plug is within the container-shaped conductive structure. Some embodiments include methods of forming conductive interconnects within integrated assemblies.

公开(公告)号：US11812610B2

公开(公告)日：2023-11-07

申请号：US16539700

申请日：2019-08-13

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Rita J. Klein ,  Jordan D. Greenlee

IPC: H10B43/35 ,  H10B43/27 ,  H10B41/27 ,  H10B41/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: Electronic devices (e.g., semiconductor devices, which may be configured for 3D NAND memory devices), comprise pillars extending through a stack of alternating conductive tiers and insulative tiers. The conductive tiers, which may include control gates for access lines (e.g., word lines), include conductive rails along an outer sidewall of the conductive tiers, distal from the pillars extending through the conductive tiers. The conductive rails protrude laterally beyond outer sidewalls of the insulative tiers. The conductive rails increase the amount of conductive material that may otherwise be in the conductive tiers, which may enable the conductive material to exhibit a lower electrical resistance, improving operational performance of the electronic devices.

公开(公告)号：US20230290721A1

公开(公告)日：2023-09-14

申请号：US17689527

申请日：2022-03-08

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Jiewei Chen ,  Sijia Yu ,  Chieh Hsien Quek ,  Rita J. Klein ,  Nancy M. Lomeli

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5226 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20230290409A1

公开(公告)日：2023-09-14

申请号：US17654311

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  John D. Hopkins ,  Jiewei Chen ,  Jordan D. Greenlee

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768

CPC classification number: G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/76843

Abstract: A microelectronic device includes a stack structure, slot structures, and dielectric material. The stack structure includes blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. At least one of the blocks includes an array region including strings of memory cells, and a staircase region including a crest sub-region interposed between a staircase structure and the array region. An uppermost boundary of the tiers within the crest sub-region underlies an uppermost boundary of the tiers within the array region. The slot structures are interposed between the blocks of the stack structure. The dielectric material extends over and between the blocks of the stack structure. A thickness of a portion of the dielectric material overlying the crest sub-region is greater than a thickness of an additional portion of the dielectric material overlying the array region. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11706918B2

公开(公告)日：2023-07-18

申请号：US16918392

申请日：2020-07-01

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins

IPC: H01L29/792 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H01L21/311

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H01L21/31111

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Conducting material is formed in one of the first tiers. The conducting material comprises a seam in and longitudinally-along opposing sides of individual of the memory-block regions in the one first tier. The seam is penetrated with a fluid that forms intermediate material in the seam longitudinally-along the opposing sides of the individual memory-block regions in the one first tier and comprises a different composition from that of the conducting material. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11705500B2

公开(公告)日：2023-07-18

申请号：US17180312

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H01L29/4966 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20230154856A1

公开(公告)日：2023-05-18

申请号：US18157962

申请日：2023-01-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Everett A. McTeer ,  Yiping Wang ,  Rajesh Balachandran ,  Rita J. Klein ,  Yongjun J. Hu

IPC: H01L23/538 ,  H01L23/532 ,  H01L21/768 ,  G11C5/06 ,  G11C5/02 ,  H01L27/06

CPC classification number: H01L23/5386 ,  H01L23/5385 ,  H01L23/5384 ,  H01L23/53204 ,  H01L21/76877 ,  G11C5/06 ,  G11C5/025 ,  H01L21/76802 ,  H01L27/0688

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of 3-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11646206B2

公开(公告)日：2023-05-09

申请号：US17101950

申请日：2020-11-23

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Brian Beatty ,  John Mark Meldrim ,  Yongjun Jeff Hu ,  Jordan D. Greenlee

IPC: H01L21/02 ,  C23C16/28 ,  C01G41/00

CPC classification number: H01L21/02645 ,  C01G41/00 ,  C23C16/28 ,  H01L21/0257 ,  C01P2006/40

Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.

公开(公告)号：US11600630B2

公开(公告)日：2023-03-07

申请号：US16988156

申请日：2020-08-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Nancy M. Lomeli ,  John D. Hopkins ,  Jiewei Chen ,  Indra V. Chary ,  Jun Fang ,  Vladimir Samara ,  Kaiming Luo ,  Rita J. Klein ,  Xiao Li ,  Vinayak Shamanna

IPC: H01L27/11568 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L21/306 ,  G11C16/04 ,  G11C5/02

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230055319A1

公开(公告)日：2023-02-23

申请号：US17409300

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Collin Howder ,  Jordan D. Greenlee

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition. from that of the insulative material in the upper second tier that is laterally-between the lines. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion. Other embodiments, including structure independent of method, are disclosed.