公开(公告)号：US06876023B2

公开(公告)日：2005-04-05

申请号：US10158851

申请日：2002-06-03

申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0433 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78642

摘要： A semiconductor memory element subject to a threshold voltage controlling method other than those based on low leak currents or on the implantation of impurities. Such semiconductor elements are used to form semiconductor memory elements that are employed in scaled-down structures and are conducive to high-speed write operations thanks to a sufficiently prolonged refresh cycle. These semiconductor memory elements are in turn used to constitute a semiconductor memory device. A very thin semiconductor film is used as channels so that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. An amount of electrical charges in each charge accumulating region is used to change conductance between a source and a drain region of each read transistor structure, the conductance change being utilized for data storage. A channel of a transistor for electrically charging or discharging each charge accumulating region is made of a semiconductor film 5 nm thick at most. The arrangement affords both high-speed data write performance and an extended data retention time. The invention provides a high-speed, power-saving semiconductor device of high integration particularly advantageous for producing a small-scale system of low-power dissipation.

摘要翻译： 除了基于低泄漏电流或杂质注入以外的阈值电压控制方法的半导体存储元件。 这样的半导体元件用于形成在缩小结构中使用的半导体存储器元件，并且由于足够长的刷新周期而有利于高速写入操作。 这些半导体存储元件又用于构成半导体存储器件。 使用非常薄的半导体膜作为通道，使得通过膜厚度方向的量子力学容纳效应来降低泄漏电流。 使用每个电荷累积区域中的电荷量来改变每个读取晶体管结构的源区和漏区之间的电导，所述电导变化用于数据存储。 用于对每个电荷累积区进行充电或放电的晶体管的沟道由最多为5nm厚的半导体膜制成。 该方案具有高速数据写入性能和扩展数据保留时间。 本发明提供了高集成度的高速，省电的半导体器件，特别有利于生产低功耗的小规模系统。

公开(公告)号：US06849895B2

公开(公告)日：2005-02-01

申请号：US09944073

申请日：2001-09-04

申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L27/108

CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

公开(公告)号：US06588348B2

公开(公告)日：2003-07-08

申请号：US10035331

申请日：2002-01-04

申请人： Yasuhiro Nomura ,  Kazuo Yano

发明人： Yasuhiro Nomura ,  Kazuo Yano

IPC分类号： E05G100

CPC分类号： F15B15/16 ,  E05G1/00

摘要： Disclosed is an inexpensive money safe which is safe against fire and the like and which can easily be utilized when necessary. A basement (10) for accommodating a movable money safe (1) is accommodated in the basement (10), and upper surface of the movable money safe (1) is covered with a fireproof lid (15) which is the same color as that of the floor (12), and if the movable money safe (1) is driven into the room interior (11) for utilizing the movable cylinder unit (20) which is operated with water pressure of running water to drive the movable money safe (1) into the room interior (11).

摘要翻译： 公开了一种廉价的货币保险箱，其在防火等方面是安全的，并且在必要时可以容易地利用。 用于容纳可移动货币保险箱（1）的地下室（10）容纳在地下室（10）中，并且可移动货币保险箱（1）的上表面覆盖有与该颜色相同颜色的防火盖（15） （12），并且如果可移动货币保险箱（1）被驱动到房间内部（11）中，以利用以自来水的水压运行的可动缸单元（20）来驱动可动钱保险箱 1）进入房间内部（11）。

公开(公告)号：US06337293B1

公开(公告)日：2002-01-08

申请号：US09332445

申请日：1999-06-14

申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

IPC分类号： H01L2100

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/685 ,  H01L29/7883 ,  Y10S438/962

摘要： A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise. In order to accomplish this a control electrode is formed so as to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile memory device can be realized with reduced size. A method of forming a memory element is also disclosed including performing the following steps of forming a first insulating layer, a second insulating layer, a first conductive layer and a layer of amorphous silicon. The amorphous silicon layer is crystallized to a polycrystalline silicon film. Semiconductor drains are deposited to form charge trapping and storage regions. A fourth insulating layer is deposited over the drains and a second conductive layer is deposited over a layer of silicon dioxide to form a control electrode of the memory element.

摘要翻译： 公开了一种半导体量子存储器元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且抵抗噪声。 为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。 因此，该元件可以具有小尺寸并且可以高密度地存储信息。 因此，可以以减小的尺寸实现高度集成的低功耗非易失性存储器件。 还公开了一种形成存储元件的方法，包括执行以下步骤：形成第一绝缘层，第二绝缘层，第一导电层和非晶硅层。 非晶硅层结晶成多晶硅膜。 沉积半导体漏极以形成电荷捕获和存储区域。 在漏极上沉积第四绝缘层，并且在二氧化硅层上沉积第二导电层以形成存储元件的控制电极。

公开(公告)号：US06194759B1

公开(公告)日：2001-02-27

申请号：US09436225

申请日：1999-11-09

申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

IPC分类号： H01L2976

CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/08 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888

摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

公开(公告)号：US6040605A

公开(公告)日：2000-03-21

申请号：US236630

申请日：1999-01-26

申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888 ,  G11C2216/08

摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

公开(公告)号：US5960266A

公开(公告)日：1999-09-28

申请号：US878206

申请日：1997-06-18

申请人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

发明人： Tomoyuki Ishii ,  Kazuo Yano ,  Koichi Seki ,  Toshiyuki Mine ,  Takashi Kobayashi

IPC分类号： H01L27/115 ,  H01L27/12 ,  H01L29/68 ,  H01L29/788 ,  H01L21/00 ,  H01L21/31 ,  H01L21/469 ,  H01L21/84

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/685 ,  H01L29/7883 ,  Y10S438/962

摘要： A quantum semiconductor memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is resistant to interference from noises. In order to accomplish this a control electrode is formed to cover the entirety of thin film regions connecting low-resistance regions. As a result, the element can have a small size and can store information with high density. Thus, a highly integrated, low power consumption non-volatile quantum memory device can be realized with reduced size.

摘要翻译： 公开了一种量子半导体存储元件，其可以容易地在多个存储元件之间共享端子，并且可以通过高电流并且能够抵抗来自噪声的干扰。 为了实现这一点，形成控制电极以覆盖连接低电阻区域的整个薄膜区域。 因此，该元件可以具有小尺寸并且可以高密度地存储信息。 因此，可以以减小的尺寸实现高度集成的低功耗非易失性量子存储器件。

公开(公告)号：US5107141A

公开(公告)日：1992-04-21

申请号：US604454

申请日：1990-10-29

申请人： Kazuo Yano ,  Mitsuru Hiraki ,  Hisayuki Higuchi ,  Suguru Tachibana ,  Makoto Suzuki ,  Katsuhiro Shimohigashi

发明人： Kazuo Yano ,  Mitsuru Hiraki ,  Hisayuki Higuchi ,  Suguru Tachibana ,  Makoto Suzuki ,  Katsuhiro Shimohigashi

IPC分类号： H03K19/00 ,  H03K19/013 ,  H03K19/0944

CPC分类号： H03K19/0013 ,  H03K19/0136 ,  H03K19/09448

摘要： An output circuit portion of a BiCMOS logic circuit adapted to operating on a low voltage has an npn transistor Q5 connected between the power source Vcc and an output N6, and has an npn transistor Q6 connected between the output N6 and ground potential GND. The base of the npn transistor Q5 is driven by the drain output of p-channel MOSFETs MP3, MP4, and the base of the npn transistor Q6 is driven by the drain output of p-channel MOSFET QP5. When the power source voltage Vcc drops, the voltage applied between the drain and the source of MOSFET MP5 becomes small by the effect of V.sub.BE of the transistor Q6, but the drain current of the MOSFET MP5 changes little. Therefore, the BiCMOS circuit operates at high speeds (see FIG. 1) even when the power source voltage drops.

摘要翻译： 适用于低电压工作的BiCMOS逻辑电路的输出电路部分具有连接在电源Vcc和输出N6之间的npn晶体管Q5，并具有连接在输出N6和地电位GND之间的npn晶体管Q6。 npn晶体管Q5的基极由p沟道MOSFET MP3，MP4的漏极输出驱动，npn晶体管Q6的基极由p沟道MOSFET QP5的漏极输出驱动。 当电源电压Vcc下降时，通过晶体管Q6的VBE的影响，施加在MOSFET MP5的漏极和源极之间的电压变小，但MOSFET MP5的漏极电流变化较小。 因此，即使当电源电压下降时，BiCMOS电路也以高速工作（参见图1）。

公开(公告)号：US5041892A

公开(公告)日：1991-08-20

申请号：US522826

申请日：1990-05-14

申请人： Kazuo Yano ,  Masaaki Aoki ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi

发明人： Kazuo Yano ,  Masaaki Aoki ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/36 ,  H01L29/66 ,  H01L29/732

CPC分类号： H01L29/66992 ,  H01L27/0623 ,  H01L29/36

摘要： In a homo-junction bipolar transistor suitable for a low temperature operation below 200 K. (particularly below 77 K.), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3 and the impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and a high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.

公开(公告)号：US09486161B2

公开(公告)日：2016-11-08

申请号：US14124067

申请日：2011-06-07

申请人： Koji Ara ,  Tomoaki Akitomi ,  Kazuo Yano

发明人： Koji Ara ,  Tomoaki Akitomi ,  Kazuo Yano

IPC分类号： G01P15/00 ,  G01P11/00 ,  A61B5/11 ,  G06F19/00

CPC分类号： A61B5/11 ,  A61B5/1123 ,  G01P15/00 ,  G06F19/3481

摘要： An information processing system includes a sensor node and a server. The sensor node obtains acceleration data and transmits the data to the server. The server obtains and records the number of zero crossings from the acceleration data. The server obtains and records the frequency distribution of the number of zero crossings. The server obtains one or more of the following: the slope of the approximate line of the distribution; the linearity of the distribution; the inflection point; the slope of the approximate line in the zero crossing range below the inflection point; the slope of the approximate line in the zero crossing range above the inflection point; the linearity of the distribution in the zero crossing range below the inflection point; and the linearity of the distribution in the zero crossing range above the inflection point. Then, the server records the obtained value.

摘要翻译： 信息处理系统包括传感器节点和服务器。 传感器节点获取加速度数据并将数据发送到服务器。 服务器从加速度数据中获取并记录过零点数。 服务器获取并记录过零点数的频率分布。 服务器获得以下一个或多个：分布的近似线的斜率; 分布的线性; 拐点; 在零拐点的拐点以下的近似线的斜率; 在拐点上方的过零点的近似线的斜率; 在零拐点低于拐点处的分布线性度; 以及在拐点上方的零交叉点的分布的线性。 然后，服务器记录获取的值。