公开(公告)号：US20170141189A1

公开(公告)日：2017-05-18

申请号：US14941664

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/265 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L29/1083 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET includes a substrate, a plurality of insulators disposed on the substrate, a gate stack and a strained material. The substrate includes at least one semiconductor fin and the semiconductor fin includes at least one modulation portion distributed therein. The semiconductor fin is sandwiched by the insulators. The gate stack is disposed over portions of the semiconductor fin and over portions of the insulators. The strained material covers portions of the semiconductor fin that are revealed by the gate stack. In addition, a method for fabricating the FinFET is provided.

公开(公告)号：US09653605B2

公开(公告)日：2017-05-16

申请号：US14517310

申请日：2014-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhe-Hao Zhang ,  Tung-Wen Cheng ,  Chang-Yin Chen ,  Che-Cheng Chang ,  Yung-Jung Chang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/306 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7848

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.

公开(公告)号：US09614089B2

公开(公告)日：2017-04-04

申请号：US14827092

申请日：2015-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/70 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L21/28247 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a protection element over the gate stack. A top of the protection element is wider than a bottom of the protection element. The semiconductor device structure also includes a spacer element over a side surface of the protection element and a sidewall of the gate stack. The semiconductor device structure further includes a conductive contact electrically connected to a conductive feature over the semiconductor substrate.

公开(公告)号：US09608113B2

公开(公告)日：2017-03-28

申请号：US14930037

申请日：2015-11-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Yi-Jen Chen ,  Yung-Jung Chang

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/165

CPC classification number: H01L21/823814 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The semiconductor device structure also includes a sealing structure over a sidewall of the gate stack, and a width ratio of the sealing structure to the gate stack is in a range from about 0.05 to about 0.7. The semiconductor device structure further includes an etch stop layer over the semiconductor substrate, the gate stack, and the sealing structure. The etch stop layer is in contact with the sealing structure.

公开(公告)号：US09564528B2

公开(公告)日：2017-02-07

申请号：US14749597

申请日：2015-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Cheng-Yen Yu ,  Che-Cheng Chang ,  Tung-Wen Cheng ,  Zhe-Hao Zhang ,  Bo-Feng Young

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/267 ,  H01L29/08 ,  H01L29/06 ,  H01L29/165 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. An isolation insulating layer is formed so that an upper part of the fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the fin structure. Recesses are formed in the isolation insulating layer at both sides of the fin structure. A recess is formed in a portion of the fin structure which is not covered by the gate structure. The recess in the fin structure and the recesses in the isolation insulating layer are formed such that a depth D1 of the recess in the fin structure and a depth D2 of the recesses in the isolation insulating layer measured from an uppermost surface of the isolation insulating layer satisfy 0≦D1≦D2 (but D1 and D2 are not zero at the same time).

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成翅片结构。 隔离绝缘层形成为使得翅片结构的上部从隔离绝缘层突出。 在鳍结构的一部分上形成栅极结构。 在翅片结构的两侧的隔离绝缘层中形成凹部。 在翅片结构的未被栅极结构覆盖的部分中形成凹部。 翅片结构中的凹部和隔离绝缘层中的凹部被形成为使得翅片结构中的凹部的深度D1和隔离绝缘层中的凹部的深度D2从隔离绝缘层的最上表面测量 满足0≤D1≤D2（但D1和D2同时不为零）。

公开(公告)号：US09559100B2

公开(公告)日：2017-01-31

申请号：US15086433

申请日：2016-03-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/31055 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681

Abstract: A semiconductor device includes first and second Fin FET transistors and a separation plug made of an insulating material and disposed between the first and second Fin FET transistors. The first Fin FET transistor includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction. The second Fin FET transistor includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending the second direction. In across section along the second direction and across the first gate electrode, the second gate electrode and the separation plug, the separation plug has a tapered shape having atop size smaller than a bottom size.

Abstract translation: 半导体器件包括第一和第二Fin FET晶体管和由绝缘材料制成并分布在第一和第二Fin FET晶体管之间的分离插头。 第一Fin FET晶体管包括在第一方向上延伸的第一鳍结构，形成在第一鳍结构上的第一栅极电介质和形成在第一栅极电介质上并且垂直于第一方向延伸的第二方向的第一栅电极。 第二鳍FET晶体管包括第二鳍结构，形成在第二鳍结构上的第二栅极电介质和形成在第一栅极电介质上并延伸第二方向的第二栅电极。 在沿着第二方向跨过第一栅电极，第二栅电极和分离塞的横截面中，分离塞具有顶部尺寸小于底部尺寸的锥形形状。

公开(公告)号：US20250169101A1

公开(公告)日：2025-05-22

申请号：US19027821

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H10D30/62 ,  G01N21/88 ,  H01L21/3213 ,  H01L21/66 ,  H01L21/67 ,  H10D30/01 ,  H10D64/27 ,  H10D64/66 ,  H10D64/68 ,  H10D84/01 ,  H10D84/03

Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

公开(公告)号：US12176424B2

公开(公告)日：2024-12-24

申请号：US17671230

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/94

Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

公开(公告)号：US20240379826A1

公开(公告)日：2024-11-14

申请号：US18782065

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

公开(公告)号：US11842932B2

公开(公告)日：2023-12-12

申请号：US17739899

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/82385 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/30608 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795

Abstract: A method includes providing a substrate having a channel region, forming a gate stack layer over the channel region, forming a patterned hard mask over the gate stack layer, etching a top portion of the gate stack layer through openings in the patterned hard mask with a first etchant, etching a middle portion and a bottom portion of the gate stack layer with a second etchant that includes a passivating gas. A gate stack is formed with a passivation layer deposited on sidewalls of the gate stack. The method also includes etching the gate stack with a third etchant, thereby removing a bottom portion of the passivation layer and recessing a bottom portion of the gate stack.