公开(公告)号：US09891927B2

公开(公告)日：2018-02-13

申请号：US14281551

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Stephan Gaskins

IPC: G06F1/00 ,  H04L29/06 ,  G06F9/38 ,  G06F1/32 ,  G06F12/084 ,  G06F13/24 ,  G06F9/44 ,  G06F13/364 ,  G06F12/0808 ,  G06F9/30 ,  G06F12/0875 ,  G06F1/04 ,  G06F1/12 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  H04L9/08

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores.

公开(公告)号：US09767288B2

公开(公告)日：2017-09-19

申请号：US15338598

申请日：2016-10-31

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F21/57 ,  H04L9/06

CPC classification number: G06F21/572 ,  G06F2221/2139 ,  H04L9/0631 ,  H04L9/0643

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), a tamper detector, a random number generator, and a JTAG control chain. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest, where the encrypted message digest has an encrypted version of a first message digest that corresponds to the BIOS contents. The tamper detector is operatively coupled to the BIOS ROM, and is configured to generate a BIOS check interrupt at a combination of prescribed intervals and event occurrences, and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest, and is configured to compare the second message digest with the decrypted message digest, and is configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal, where the event occurrences include input/output accesses. The random number generator disposed within the microprocessor, and generates a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby the prescribed intervals are randomly varied. The JTAG control chain is configured to program the combination of prescribed intervals and event occurrences within tamper detection microcode storage.

公开(公告)号：US09471133B2

公开(公告)日：2016-10-18

申请号：US14281758

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F12/08 ,  G06F1/32 ,  G06F1/04 ,  G06F1/12 ,  G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F13/24

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of processing cores, a service processing unit and a memory accessible by both the service processing unit and the plurality of processing cores. At least one of the plurality of processing cores is configured to write a patch to the memory. The patch comprises one or more instructions to be fetched from the memory and executed by the service processing unit after written to the memory by the at least one of the plurality of processing cores.

Abstract translation: 微处理器包括多个处理核心，服务处理单元和可由服务处理单元和多个处理核心访问的存储器。 多个处理核心中的至少一个被配置为将补丁写入存储器。 所述补丁包括要从所述存储器中取出并由所述服务处理单元在由所述多个处理核心中的至少一个写入所述存储器之后执行的一个或多个指令。

公开(公告)号：US09461818B2

公开(公告)日：2016-10-04

申请号：US14066350

申请日：2013-10-29

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC: G06F11/30 ,  H04L9/08 ,  G06F12/08 ,  G06F21/52 ,  G06F21/71 ,  G06F21/72 ,  G06F9/30 ,  G06F21/60 ,  H04L9/06 ,  G06F21/54

CPC classification number: H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program includes receiving an object file specifying an unencrypted program that includes conventional branch instructions whose target address may be determined pre-run time. The method also includes analyzing the program to obtain chunk information that divides the program into a sequence of chunks each comprising a sequence of instructions and that includes encryption key data associated with each of the chunks. The encryption key data associated with each of the chunks is distinct. The method also includes replacing each of the conventional branch instructions that specifies a target address that is within a different chunk than the chunk in which the conventional branch instruction resides with a branch and switch key instruction. The method also includes encrypting the program based on the chunk information.

Abstract translation: 用于加密被配置为解密和执行加密程序的微处理器后续执行的程序的方法包括接收指定未加密程序的目标文件，其包括其目标地址可以被确定为预先运行时间的常规分支指令。 该方法还包括分析程序以获得将程序划分成每个包括指令序列并且包括与每个块相关联的加密密钥数据的块的序列的块信息。 与每个块相关联的加密密钥数据是不同的。 该方法还包括用分支和切换键指令代替指定与常规分支指令所在的块不同的块内的目标地址的每个常规分支指令。 该方法还包括基于块信息来加密程序。

公开(公告)号：US09317301B2

公开(公告)日：2016-04-19

申请号：US14526029

申请日：2014-10-28

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC: G06F9/445 ,  G06F9/28 ,  G06F9/44 ,  G06F9/30 ,  G06F9/26 ,  G06F9/38 ,  G06F15/82

CPC classification number: G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

Abstract: A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. In response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions.

Abstract translation: 微处理器包括保持微处理器架构状态的多个寄存器和指示微处理器的引导指令集体系结构（ISA）作为x86 ISA或高级RISC机器（ARM）ISA的指示符。 微处理器还包括硬件指令转换器，将x86 ISA指令和ARM ISA指令转换为微指令。 作为引导ISA的指令，硬件指令转换器将转换为接收复位信号后微处理器从架构存储器空间中提取的初始ISA指令。 微处理器还包括耦合到硬件指令转换器的执行流水线。 执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。 响应于复位信号，微处理器在获取初始ISA指令之前初始化由引导ISA定义的多个寄存器中的架构状态。

公开(公告)号：US09129113B2

公开(公告)日：2015-09-08

申请号：US14079226

申请日：2013-11-13

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F12/14 ,  G06F21/57

CPC classification number: G06F21/572 ,  G06F21/575 ,  G06F21/64

Abstract: An apparatus including a ROM, a selector, and a detector. The ROM has partitions and encrypted digests. Each of the partitions is stored as plaintext, and each of the encrypted digests includes an encrypted version of a first digest associated with a corresponding one of the partitions. The selector selects one or more of the partitions responsive to an interrupt. The detector accesses the one or more of the partitions and corresponding one or more of the encrypted digests upon assertion of the interrupt, and directs a microprocessor to generate one or more of second digests corresponding to the one or more of the partitions and one or more of decrypted digests corresponding to the one or more of encrypted digests using the same algorithms and key that were employed to generate the first digest and the encrypted digests, and compares the one or more of the second digests with the one or more of the decrypted digests, and precludes operation of the microprocessor if the one or more of the second digests and the one or more of the decrypted digests are not pair wise equal.

Abstract translation: 一种包括ROM，选择器和检测器的装置。 ROM具有分区和加密摘要。 每个分区被存储为明文，并且每个加密的摘要包括与相应的一个分区相关联的第一摘要的加密版本。 选择器响应于中断选择一个或多个分区。 检测器在断言时访问一个或多个分区和对应的一个或多个加密摘要，并指示微处理器生成对应于一个或多个分区和一个或多个分区的一个或多个第二摘要 使用与用于生成第一摘要和加密摘要相同的算法和密钥对应于一个或多个加密摘要的解密摘要，并将第二摘要中的一个或多个与解密的摘要中的一个或多个进行比较 并且如果所述第二摘要中的一个或多个和所解密的摘要中的一个或多个不是成对相等的，则排除所述微处理器的操作。

公开(公告)号：US20150212947A1

公开(公告)日：2015-07-30

申请号：US14188905

申请日：2014-02-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Stephan Gaskins

IPC: G06F12/08 ,  G06F1/32

CPC classification number: G06F12/0891 ,  G06F1/3203 ,  G06F1/3215 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/50 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/0893 ,  G06F2212/6082 ,  Y02D10/152 ,  Y02D50/20

Abstract: A microprocessor includes a cache memory and a control module. The control module makes the cache size zero and subsequently make it between zero and a full size of the cache, counts a number of evictions from the cache after making the size between zero and full and increase the size when the number of evictions reaches a predetermined number of evictions. Alternatively, a microprocessor includes: multiple cores, each having a first cache memory; a second cache memory shared by the cores; and a control module. The control module puts all the cores to sleep and makes the second cache size zero and receives a command to wakeup one of the cores. The control module counts a number of evictions from the first cache of the awakened core after receiving the command and makes the second cache size non-zero when the number of evictions reaches a predetermined number of evictions.

Abstract translation: 微处理器包括高速缓冲存储器和控制模块。 控制模块使高速缓存大小为零，随后将其设置在零和高速缓存的完整大小之间，在将大小从零到满之后，从高速缓存中计数一些驱逐，并且当驱逐次数达到预定时增加大小 驱逐次数 或者，微处理器包括：多个核，每个具有第一高速缓冲存储器; 由核心共享的第二缓存存储器; 和控制模块。 控制模块将所有内核置于休眠状态，并使第二个缓存大小为零，并接收一个命令以唤醒其中一个内核。 控制模块在接收到命令之后对来自唤醒的核心的第一高速缓存进行计数，并且当驱逐次数达到预定的驱逐次数时使第二高速缓存大小不为零。

公开(公告)号：US20150134975A1

公开(公告)日：2015-05-14

申请号：US14079087

申请日：2013-11-13

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F21/57

CPC classification number: G06F21/572 ,  G06F2221/2139

Abstract: An apparatus including a ROM and a microprocessor. The ROM includes BIOS contents that are stored as plaintext and an encrypted digest. The encrypted digest includes an encrypted version of a first digest corresponding to the BIOS contents. The microprocessor is coupled to the BIOS ROM, and includes a tamper timer and a tamper detector. The tamper timer periodically generates an interrupt at a prescribed interval. The tamper detector accesses the BIOS contents and the encrypted digest upon assertion of the interrupt, and directs the microprocessor to generate a second digest corresponding to the BIOS contents and a decrypted digest corresponding to the encrypted digest using the same algorithms and key that were employed to generate the first digest and the encrypted digest, and compares the second digest with the decrypted digest, and precludes operation of the microprocessor if the second digest and the decrypted digest are not equal.

Abstract translation: 一种包括ROM和微处理器的装置。 ROM包括存储为明文和加密摘要的BIOS内容。 加密摘要包括对应于BIOS内容的第一摘要的加密版本。 微处理器耦合到BIOS ROM，并且包括篡改定时器和篡改检测器。 篡改定时器周期性地以规定的间隔产生中断。 篡改检测器在断言时访问BIOS内容和加密摘要，并引导微处理器使用与使用相同的算法和密钥来生成对应于BIOS内容的第二摘要和对应于加密摘要的解密摘要 生成第一个摘要和加密的摘要，并将第二个摘要与解密的摘要进行比较，如果第二个摘要和解密的摘要不相等，则排除微处理器的操作。

公开(公告)号：US20150113250A1

公开(公告)日：2015-04-23

申请号：US14088620

申请日：2013-11-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30178 ,  G06F9/328 ,  G06F9/3891

Abstract: A microprocessor includes a plurality of memories each configured to hold microcode instructions. At least a first of the plurality of memories is configured to provide M-bit wide words of compressed microcode instructions, and at least a second of the plurality of memories is configured to provide N-bit wide words of uncompressed microcode instructions. M and N are integers greater than zero and N is greater than M. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the at least a first of the plurality of memories and before being executed.

Abstract translation: 微处理器包括多个存储器，每个存储器被配置为保持微码指令。 所述多个存储器中的至少第一个被配置为提供压缩微码指令的M位宽的字，并且所述多个存储器中的至少一个存储器被配置为提供未压缩的微代码指令的N位宽字。 M和N是大于零并且N大于M的整数。微处理器还包括解压缩单元，其被配置为在从多个存储器中的至少第一个存储器中取出并在执行之前解压缩压缩的微代码指令。

公开(公告)号：US09009512B2

公开(公告)日：2015-04-14

申请号：US14172373

申请日：2014-02-04

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Darius D. Gaskins

IPC: G06F1/32 ,  G06F1/26 ,  G06F9/50

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22

Abstract: A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications.

Abstract translation: 多核处理器包括分布在每个核心中的微码，使得每个核心能够参与去集中的核心间状态发现过程。 在相关的微代码实现方法中，多核处理器的状态由参与去集中式核心状态发现过程的至少两个核心发现。 通过在每个参与核心上执行的微代码和通过边带非系统总线通信线路在核心之间交换的信号的组合来执行核心间状态发现处理。 发现过程不受任何集中式非核心逻辑的介入。 适用的可发现状态包括目标和复合功率状态，是否启用了多少核心，启用各种资源的可用性和分布，以及核心的分层结构和协调系统。 核心状态发现过程可以根据涉及链接的核心间通信的各种分层协调系统来执行。