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公开(公告)号：US20230305915A1
公开(公告)日：2023-09-28
申请号：US18092556
申请日：2023-01-03
Applicant: Rambus Inc.
Inventor： Thomas J. GIOVANNINI , Catherine CHEN , Scott C. BEST , John Eric LINSTADT , Frederick A. WARE
CPC classification number: G06F11/079 , G06F11/073 , G06F11/0772 , G06F13/00 , G11C5/04 , G11C7/20 , G11C8/12 , G11C29/26 , G11C29/44
Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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公开(公告)号：US20230297151A1
公开(公告)日：2023-09-21
申请号：US18068437
申请日：2022-12-19
Applicant: Rambus Inc.
Inventor： Deborah Lindsey Dressler , Julia Kelly Cline , Wayne Frederick Ellis
IPC: G06F1/28 , G11C5/06 , G06F1/3287 , G06F1/3234 , G06F13/42
CPC classification number: G06F1/28 , G06F1/3275 , G06F1/3287 , G06F13/4273 , G11C5/063
Abstract: A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.
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公开(公告)号：US11762737B2
公开(公告)日：2023-09-19
申请号：US17956516
申请日：2022-09-29
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , Lawrence Lai
CPC classification number: G06F11/1076 , G06F11/1048
Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.
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公开(公告)号：US11755521B2
公开(公告)日：2023-09-12
申请号：US17809688
申请日：2022-06-29
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
CPC classification number: G06F13/4022 , G06F12/00 , G06F13/00 , G06F13/1673 , G06F13/1694
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
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公开(公告)号：US11755508B2
公开(公告)日：2023-09-12
申请号：US17507588
申请日：2021-10-21
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely Tsern , John Eric Linstadt , Thomas J. Giovannini , Craig E. Hampel , Scott C. Best , John Yan
IPC: G06F13/16
CPC classification number: G06F13/1678 , G06F13/1673 , G06F13/1694
Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.
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Patent Agency Ranking
公开(公告)号：US20230282266A1
公开(公告)日：2023-09-07
申请号：US18181185
申请日：2023-03-09
Applicant: Rambus Inc.
Inventor： Wayne F. Ellis , Wayne S. Richardson , Akash Bansal , Frederick A. Ware , Lawrence Lai , Kishore Ven Kasamsetty
IPC: G11C11/406 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C29/02 , G06F1/3234 , G11C11/4074
CPC classification number: G11C11/40615 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C29/022 , G11C29/028 , G06F1/3234 , G11C11/4074
Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
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公开(公告)号：US11750426B2
公开(公告)日：2023-09-05
申请号：US17864100
申请日：2022-07-13
Applicant: Rambus Inc.
Inventor： Kamran Farzan , Dongyun Lee
Abstract: A signal transmitter circuit includes an output driver circuit configured to transmit a signal using a multi-level pulse amplitude modulation (PAM) scheme comprising a plurality of discreet signal levels. During operation, the output driver initiates a first transition of the signal to a first level of the multi-level PAM scheme from a second level of the multi-level PAM scheme, and initiates a second transition of the signal to the first level from a third level of the multi-level PAM scheme. The signal transmitter further includes a control circuit configured to control a slew rate of the signal transmitter circuit to cause the signal to reach a threshold voltage level at a first time, the first time occurring a first duration of time after the first transition is initiated, and to cause the signal to reach the threshold voltage level at a second time, the second time occurring the first duration of time after the second transition is initiated.
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公开(公告)号：US11750359B2
公开(公告)日：2023-09-05
申请号：US17676425
申请日：2022-02-21
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe
CPC classification number: H04L7/0332 , H04L7/0008 , H04L7/0033 , H04L7/0037
Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.
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109.发明公开公开(公告)号：US20230266385A1
公开(公告)日：2023-08-24
申请号：US18157344
申请日：2023-01-20
Applicant: Rambus Inc.
Inventor： Frederick A. Ware
CPC classification number: G01R31/2882 , G01R31/31726 , G11C29/022 , G11C29/12015 , G11C29/16 , G11C29/50012 , G01R31/2607 , H03L7/00 , G11C2029/0401
Abstract: A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.
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公开(公告)号：US11735287B2
公开(公告)日：2023-08-22
申请号：US18074188
申请日：2022-12-02
Applicant: Rambus Inc.
Inventor： Scott C. Best , John Eric Linstadt , Paul William Roukema
CPC classification number: G11C29/4401 , G11C5/04 , G11C11/401 , G11C29/022 , G11C29/52 , G11C29/76 , G11C29/783 , G11C29/88 , G11C2029/4402
Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
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