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    MEMORY DEVICE
    101.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20240096424A1

    公开(公告)日：2024-03-21

    申请号：US18306654

    申请日：2023-04-25

    申请人： Kioxia Corporation

    发明人： Takuya FUTATSUYAMA ,  Kenichi ABE

    IPC分类号： G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H10B41/27 ,  H10B41/35

    CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H10B41/27 ,  H10B41/35

    摘要： A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.

    SEMICONDUCTOR MEMORY DEVICE
    102.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240096419A1

    公开(公告)日：2024-03-21

    申请号：US18524458

    申请日：2023-11-30

    申请人： Kioxia Corporation

    发明人： Hiroshi MAEJIMA

    IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/28 ,  G11C16/34

    CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  G11C16/32

    摘要： A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

    SEMICONDUCTOR MEMORY DEVICE
    105.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240087656A1

    公开(公告)日：2024-03-14

    申请号：US18332753

    申请日：2023-06-12

    申请人： Kioxia Corporation

    发明人： Katsuaki ISOBE ,  Takeshi HIOKA ,  Mario SAKO

    IPC分类号： G11C16/26 ,  G11C16/04

    CPC分类号： G11C16/26 ,  G11C16/0483

    摘要： A semiconductor memory device includes a first memory cell transistor, a first bit line electrically coupled to the first memory cell transistor, a first sense amplifier, and a first latch circuit. The first sense amplifier includes a first node coupled to the first bit line, a first transistor including one end electrically coupled to the first latch circuit, a second node coupled to a gate of the first transistor, and a second transistor coupled between the first and second nodes. The second transistor is in an ON state during an operation of transferring a charge from the first bit line to the first and second nodes in accordance with data of the first memory cell transistor. The second transistor is in an OFF state during an operation of transferring data of the second node to the first latch circuit.

    Weight Calibration Check for Integrated Circuit Devices having Analog Inference Capability
    106.
    发明公开
    Weight Calibration Check for Integrated Circuit Devices having Analog Inference Capability 审中-公开

    公开(公告)号：US20240087653A1

    公开(公告)日：2024-03-14

    申请号：US17940945

    申请日：2022-09-08

    申请人： Micron Technology, Inc.

    发明人： Poorna Kale

    IPC分类号： G11C16/12 ,  G06F7/544 ,  G11C16/24 ,  G11C16/26

    CPC分类号： G11C16/12 ,  G06F7/5443 ,  G11C16/24 ,  G11C16/26

    摘要： An integrated circuit device having a mechanism to check calibration of memory cells configured to perform operations of multiplication and accumulation. The integrated circuit device programs, in a first mode, threshold voltages of first memory cells in a memory cell array to store weight data, and programs, in a second mode, threshold voltages of second memory cells in the memory cell array to store a first result of applying an operation of multiplication and accumulation to a sample input and the weight data. During a calibration check, the integrated circuit device performs the operation using the first memory cells to obtain a second result, and compares the first result, retrieved from the second memory cells, and the second result to determine whether calibration of output current characteristics of the first memory cells programmed in the first mode is corrupted.

    Method and system for accessing memory cells
    108.
    发明授权
    Method and system for accessing memory cells 有权

    公开(公告)号：US11929124B2

    公开(公告)日：2024-03-12

    申请号：US17597004

    申请日：2020-11-11

    申请人： Micron Technology, Inc.

    发明人： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

    IPC分类号： G11C7/00 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C29/52

    CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C29/52

    摘要： The present disclosure relates to a method for accessing memory cells comprising: applying an increasing read voltage with a first polarity to the plurality of memory cells; counting a number of switching memory cells in the plurality based on the applying the increasing read voltage; applying a first read voltage with the first polarity based on the number of switched memory cells reaching a threshold number; applying a second read voltage with a second polarity opposite to the first polarity; and determining that a memory cell in the plurality of memory cells has a first logic value based on the memory cell having switched during one of the applying the increasing read voltage and the applying the first read voltage or based on the memory cell not having switched during the applying the second read voltage. A related system is also disclosed.

    Storing one data value by programming a first memory cell and a second memory cell
    109.
    发明授权
    Storing one data value by programming a first memory cell and a second memory cell 有权

    公开(公告)号：US11929121B2

    公开(公告)日：2024-03-12

    申请号：US17690573

    申请日：2022-03-09

    申请人： Micron Technology, Inc.

    发明人： Umberto Di Vincenzo

    IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

    CPC分类号： G11C16/102 ,  G11C16/0433 ,  G11C16/26 ,  G11C16/30

    摘要： Apparatuses, methods, and systems for storing one data value by programming a first memory cell and a second memory cell are disclosed. The first memory cell and the second memory cell may each be programmed to a first data state, a second data state, or a third data state, and the one data value can correspond to a combination of the first data state, the second data state, or the third data state to which the first memory cell and the second memory cell are programmed, where two combinations of the first data state, the second data state, or the third data state to which the first memory cell is programmable and the first data state, the second data state, or the third data state to which the second memory cell is programmable are ineligible to correspond to the one data value.