公开(公告)号：US08301268B1

公开(公告)日：2012-10-30

申请号：US12979709

申请日：2010-12-28

申请人： Robert E. Jones ,  Tommy Cushing

发明人： Robert E. Jones ,  Tommy Cushing

IPC分类号： A61N1/00

CPC分类号： A61M25/04 ,  A61M2025/0286 ,  A61N1/0558 ,  A61N1/057 ,  A61N2001/0582

摘要： There is disclosed various embodiments of an implantable anchor for anchoring a medical lead within a patient. The implantable anchor includes a body having at least one lumen for receiving a medical lead, a cam integrated with the body and rotatable to extend into the lumen for engaging, compressing and twisting the medical lead to inhibit the movement of the lead with respect to the anchor. The body of the anchor may include at least one slot, sized and positioned to receive a portion of the lead to further facilitate the inhibition of the movement of the lead. The cam may include a handle for facilitating the rotation and locking of the cam.

摘要翻译： 公开了用于将医疗引线锚定在患者体内的可植入锚固件的各种实施例。 可植入锚固体包括具有用于接收医用引线的至少一个内腔的主体，与本体一体化并且可旋转地延伸到内腔中的凸轮，用于接合，压缩和扭转医用引线，以阻止引线相对于 锚。 锚固体的主体可以包括至少一个狭槽，其尺寸和定位成接收导线的一部分，以进一步有助于阻止引线的移动。 凸轮可以包括用于促进凸轮的旋转和锁定的手柄。

公开(公告)号：US20120266730A1

公开(公告)日：2012-10-25

申请号：US13066790

申请日：2011-04-25

申请人： Robert E. Jones ,  Robert B. Thompson

发明人： Robert E. Jones ,  Robert B. Thompson

IPC分类号： B26D5/02 ,  B26D5/12 ,  B26D7/26

CPC分类号： B26D1/29 ,  B26D1/11 ,  B26D1/34 ,  B26D1/36 ,  B26D1/42 ,  B26D1/62 ,  B26D5/12 ,  B26D7/0006 ,  B26D7/26 ,  Y10T83/263 ,  Y10T83/4653 ,  Y10T83/8748 ,  Y10T83/8858 ,  Y10T83/9459

摘要： A cutting apparatus is disclosed and which includes a cutter knife which is reciprocally moveable along a path of travel, a track member mounted adjacent to the cutter knife, and which mechanically cooperates with the cutter knife so as to define, at least in part, a first non-cutting position, and the second, cutting position for the cutter knife, and a magnet mounted on the track member and which releasably magnetically restrains the cutter knife when the cutter knife is in either of the first non-cutting position, or the second, cutting position.

摘要翻译： 公开了一种切割装置，其包括可沿着行进路径往复运动的切割刀，邻近切割刀安装的轨道构件，并且其与切割刀机械配合以至少部分地限定 第一非切割位置，以及第二切割刀具的切割位置，以及安装在轨道构件上的磁体，并且当切割刀处于第一非切割位置时可释放地磁力限制切割刀，或者 第二，切割位置。

公开(公告)号：US20120080730A1

公开(公告)日：2012-04-05

申请号：US13313806

申请日：2011-12-07

申请人： GREGORY S. SPENCER ,  Jill C. Hldreth ,  Robert E. Jones

发明人： GREGORY S. SPENCER ,  Jill C. Hldreth ,  Robert E. Jones

IPC分类号： H01L31/113

CPC分类号： G02B6/12004 ,  H01L21/76283 ,  H01L27/1203 ,  H01L31/028 ,  H01L31/112

摘要： A semiconductor structure having a transistor region and an optical device region includes a transistor in a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer. A gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and the transistor is formed in the transistor region of the semiconductor structure. A waveguide device in the optical device region and a third semiconductor layer over a portion of the second semiconductor layer.

摘要翻译： 具有晶体管区域和光学器件区域的半导体结构包括在半导体结构的第一半导体层中的晶体管，其中第一半导体层在第一绝缘层之上，第一绝缘层在第二半导体层上，并且 第二半导体层在第二绝缘层之上。 晶体管的栅极电介质与第一半导体层的顶表面物理接触，并且晶体管形成在半导体结构的晶体管区域中。 光学器件区域中的波导器件和第二半导体层的一部分上的第三半导体层。

公开(公告)号：US07993352B2

公开(公告)日：2011-08-09

申请号：US11010108

申请日：2004-12-10

申请人： Damon R. Black ,  Terry D. Daglow ,  Robert E. Jones

发明人： Damon R. Black ,  Terry D. Daglow ,  Robert E. Jones

IPC分类号： A61B19/00

CPC分类号： A61N1/0529 ,  A61B5/031 ,  A61B5/6864 ,  A61B90/11 ,  A61N1/0539

摘要： In one aspect, an apparatus is provided for securing an electrical stimulation lead in position in a person's brain. The apparatus includes a body configured to seat within a burr hole formed in the person's skull. The apparatus also includes a central elastic membrane coupled to the body and extending across a central aperture of the body. The elastic membrane includes a number of pre-formed openings provided for purposes of securing the lead in position within the brain after implantation. Each pre-formed opening may penetrate through an entire thickness of the elastic membrane. Each pre-formed opening may be selected for insertion of the lead into the brain. Each pre-formed opening is adapted to elastically expand as the lead is inserted through the pre-formed opening and positioned in the brain and is adapted to elastically contract on the lead to secure the lead in position within the brain after implantation.

摘要翻译： 一方面，提供一种用于将电刺激引线固定在人的大脑中的位置的装置。 该装置包括构造成位于形成在人的头骨中的钻孔内的主体。 该装置还包括中心弹性膜，其连接到主体并延伸穿过主体的中心孔。 弹性膜包括许多预先形成的开口，用于将植入后的铅固定在脑内的位置。 每个预成形的开口可以穿透弹性膜的整个厚度。 可以选择每个预形成的开口用于将铅插入脑中。 每个预先形成的开口适于在引线穿过预先形成的开口并且定位在大脑中时弹性膨胀，并且适于在植入之后弹性地收缩在导线上以将引线固定在大脑内的适当位置。

公开(公告)号：US20110027950A1

公开(公告)日：2011-02-03

申请号：US12510358

申请日：2009-07-28

申请人： Robert E. Jones ,  Dean J. Denning ,  Gregory S. Spencer

发明人： Robert E. Jones ,  Dean J. Denning ,  Gregory S. Spencer

IPC分类号： H01L27/12

CPC分类号： H01L27/14689 ,  H01L27/0617 ,  H01L27/14643

摘要： A method is provided for integrating a germanium photodetector with a CMOS circuit. The method comprises: forming first and second isolation regions in a silicon substrate; forming a gate electrode in the first isolation region; implanting source/drain extensions in the silicon substrate adjacent to the gate electrode; forming a first sidewall spacer on the gate electrode; implanting source/drain regions in the silicon substrate; removing the first sidewall spacer from the gate electrode; forming a first protective layer over the first and second isolation regions; removing a portion of the first protective layer to form an opening over the second isolation region; forming a semiconductor material comprising germanium in the opening; forming a second protective layer over the first and second isolation regions; selectively removing the first and second protective layers from the first isolation region; and forming contacts to the transistor and to the semiconductor material.

摘要翻译： 提供了一种用于将锗光电检测器与CMOS电路集成的方法。 该方法包括：在硅衬底中形成第一和第二隔离区; 在所述第一隔离区域中形成栅电极; 在邻近栅电极的硅衬底中注入源极/漏极延伸部分; 在所述栅电极上形成第一侧壁间隔物; 在硅衬底中注入源/漏区; 从所述栅极电极去除所述第一侧壁间隔物; 在所述第一和第二隔离区域上形成第一保护层; 去除所述第一保护层的一部分以在所述第二隔离区域上形成开口; 在开口中形成包含锗的半导体材料; 在所述第一和第二隔离区域上形成第二保护层; 从第一隔离区选择性地去除第一和第二保护层; 以及形成与晶体管和半导体材料的接触。

公开(公告)号：US07871854B1

公开(公告)日：2011-01-18

申请号：US12543619

申请日：2009-08-19

申请人： Gregory S. Spencer ,  Robert E. Jones

发明人： Gregory S. Spencer ,  Robert E. Jones

IPC分类号： H01L21/00

CPC分类号： H01L31/105 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A method includes forming a first opening in a top surface of a semiconductor substrate, performing an implant into the top surface to form a doped region, epitaxially growing a semiconductor layer in the first opening along a bottom of the first opening and along sidewalls of the first opening, wherein the epitaxially growing comprises in-situ doping the semiconductor layer, filling the first opening with a dielectric material, forming a second opening in the dielectric material, wherein a bottom of the second opening exposes the epitaxially grown semiconductor layer and sidewalls of the second opening expose the dielectric material; and filling the second opening with a semiconductor material, wherein the semiconductor material comprises a top electrode and a bottom electrode. The bottom electrode is in electrical contact with the semiconductor layer which is in electrical contact with the doped region. The doped region is laterally adjacent the semiconductor material.

摘要翻译： 一种方法包括在半导体衬底的顶表面中形成第一开口，在顶表面中进行注入以形成掺杂区域，沿着第一开口的底部沿着第一开口的底部外延生长第一开口中的半导体层， 第一开口，其中所述外延生长包括原位掺杂半导体层，用电介质材料填充第一开口，在电介质材料中形成第二开口，其中第二开口的底部露出外延生长的半导体层和侧壁 第二开口暴露电介质材料; 以及用半导体材料填充所述第二开口，其中所述半导体材料包括顶部电极和底部电极。 底部电极与与掺杂区域电接触的半导体层电接触。 掺杂区域横向邻近半导体材料。

公开(公告)号：US20100127345A1

公开(公告)日：2010-05-27

申请号：US12277519

申请日：2008-11-25

申请人： Paul W. Sanders ,  Robert E. Jones ,  Michael F. Petras ,  Chandrasekaram Ramiah

发明人： Paul W. Sanders ,  Robert E. Jones ,  Michael F. Petras ,  Chandrasekaram Ramiah

IPC分类号： H01L29/00 ,  H01L21/60

CPC分类号： H01L25/162 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/58 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0296 ,  H01L27/0629 ,  H01L28/00 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/1147 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16503 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2224/13099

摘要： 3-D ICs (18, 18′, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20). The isolator substrate (30) provides superior IPD (38) to AD (26) cross-talk attenuation while permitting each substrate (20, 30, 34) to have small high aspect ratio TSVs (40), facilitating high circuit packing density and efficient manufacturing.

摘要翻译： 通过堆叠单独预制的基板（20,30,34），通过穿通基板（20,30,34）耦合而提供具有降低的串扰和高封装密度的集成无源器件（IPD）（38）的3-D IC（18,18'，90） -vias（TSV）（40）。 有源器件（AD）衬底（20）在其上部（26）上具有接触。 隔离器基板（30）接合到AD基板（20），使得隔离器基板（30）中的TSV（4030）与AD基板（20）上的触点（26）相连，并且希望具有互连区 （44）在其上表面。 IPD衬底（34）被结合到隔离器衬底（30），使得其中的TSV（4034）耦合到隔离器衬底（30）上的互连区（44）和/或其中的TSV（4030）。 IPD（38）形成在其上表面上，并且在IPD（34）和隔离器（30）衬底中的TSV（4034,4030）与AD衬底（20）中的器件（26）耦合。 隔离器基板（30）提供优异的IPD（38）到AD（26）串扰衰减，同时允许每个基板（20,30,34）具有小的高纵横比TSV（40），有利于高电路封装密度和效率 制造业。

公开(公告)号：US20100076606A1

公开(公告)日：2010-03-25

申请号：US12376260

申请日：2007-08-23

申请人： William Stuart Gatley ,  Robert E. Jones

发明人： William Stuart Gatley ,  Robert E. Jones

IPC分类号： G05D23/19 ,  G05D7/06

CPC分类号： F04D27/004 ,  F24F11/77 ,  F24F2110/40

摘要： An airflow control system for a blower providing the combustion air for an HVAC system comprises a single phase AC blower motor driving a blower wheel within a blower housing, a vacuum sensor mounted to the housing to sense the vacuum or pressure differential created by the blower as it operates, and a controller that receives as its only feedback signal a variable signal from the vacuum sensor which signal is proportional to the sensed vacuum within the housing and provides an output voltage to the blower motor to adjust the blower motor speed to thereby preferably produce a constant air flow.

摘要翻译： 用于为HVAC系统提供燃烧空气的鼓风机的气流控制系统包括驱动鼓风机壳体内的鼓风机叶轮的单相交流送风马达，安装在壳体上的真空传感器，以感测由鼓风机产生的真空或压差 以及控制器，其接收来自真空传感器的可变信号作为其唯一反馈信号，该信号与壳体内感测的真空成比例，并且向鼓风机电机提供输出电压以调节鼓风机电机的速度，从而优选地产生 恒定的气流。

公开(公告)号：US07622313B2

公开(公告)日：2009-11-24

申请号：US11193926

申请日：2005-07-29

申请人： Robert E. Jones ,  Scott K. Pozder

发明人： Robert E. Jones ,  Scott K. Pozder

IPC分类号： H01L21/00 ,  B29C65/00

CPC分类号： H01L21/50 ,  B32B37/00 ,  H01L22/20 ,  Y10T156/10 ,  Y10T156/1052 ,  Y10T156/1062

摘要： A method of assembling an electronic device includes testing a first wafer of first die to identify the location of functional first die and dividing the first wafer into a set of panels, wherein a panel includes an M×N array of first die. A panel is bonded to a panel site of a second wafer to form a panel stack wherein a panel site defines an M×N array of second die in the second wafer. The panel stack is sawed into a devices comprising a first die bonded to a second die. Dividing the first wafer into panels may be done according statically or dynamically (to maximize the number of panels having a yield exceeding a specified threshold). Binning of the panels and panel sites according to functional die patterns may be performed to preferentially bond panels to panel sites of the same bin.

摘要翻译： 组装电子设备的方法包括测试第一晶片的第一晶片以识别功能第一裸片的位置并将第一晶片分成一组面板，其中面板包括第一裸片的MxN阵列。 面板结合到第二晶片的面板部位以形成面板堆叠，其中面板部位在第二晶片中限定第二模具的MxN阵列。 面板堆叠被锯成包括结合到第二模具的第一模具的装置。 可以将第一晶片划分成面板可以静态或动态地进行（以最大化具有超过特定阈值的产量的面板的数量）。 可以执行根据功能性模具图案的面板和面板位置的分层以优先地将面板粘合到同一箱的面板位置。

公开(公告)号：US20080182379A1

公开(公告)日：2008-07-31

申请号：US11910054

申请日：2005-03-31

申请人： Brad Smith ,  Cindy Goldberg ,  Robert E. Jones

发明人： Brad Smith ,  Cindy Goldberg ,  Robert E. Jones

IPC分类号： H01L21/76

CPC分类号： H01L21/31695 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/26 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76829 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： To improve the mechanical strength of a wafer comprising a low-k dielectric layer, the low-k dielectric layer is formed so as to have certain regions of low dielectric constant and the remainder having a higher mechanical strength. The higher-strength regions may have a relatively-higher value of dielectric constant. Selective ultraviolet curing of a dielectric material can be performed so as to expel a porogen from the region(s) desired to have low dielectric constant. A photomask, hardmask, or opaque resist, patterned so as to define the region(s) to have lower dielectric constant, is used to shield the remainder of the dielectric material from the ultraviolet radiation. Alternatively, a layer of dielectric material can be blanket cured to lower its dielectric constant, then non-critical regions thereof can be selectively over-cured whereby to produce regions of increased mechanical strength.

摘要翻译： 为了提高包含低k电介质层的晶片的机械强度，形成低k电介质层以具有低介电常数的某些区域，其余部分具有较高的机械强度。 较高强度的区域可以具有相对较高的介电常数值。 可以进行介电材料的选择性紫外线固化，以便从期望具有低介电常数的区域排出致孔剂。 使用图案化以限定具有较低介电常数的区域的光掩模，硬掩模或不透明抗蚀剂来屏蔽电介质材料的剩余部分与紫外线辐射。 或者，电介质材料层可以被覆盖固化以降低其介电常数，然后其非临界区域可以选择性地过度固化，从而产生增加的机械强度的区域。