公开(公告)号：US20150042381A1

公开(公告)日：2015-02-12

申请号：US14385436

申请日：2013-02-11

Applicant: Soitec

Inventor： Richard Ferrant

IPC: G11C16/10 ,  H03K19/177

CPC classification number: G11C16/10 ,  G11C16/045 ,  H03K19/1776

Abstract: The present invention relates to a register cell comprising one output node, at least two power supply nodes, and a first flash transistor and a second flash transistor, wherein the register cell is configured so that the output node can be driven by at least one of the power supply nodes as a function of the value stored in at least one of the flash transistors. The invention further relates to an FPGA comprising the register cell.

Abstract translation: 本发明涉及一种寄存器单元，包括一个输出节点，至少两个电源节点，以及第一闪存晶体管和第二闪存晶体管，其中该寄存器单元被配置为使得输出节点能够被至少一个 电源节点作为存储在至少一个闪存晶体管中的值的函数。 本发明还涉及包括寄存器单元的FPGA。

公开(公告)号：US20150028920A1

公开(公告)日：2015-01-29

申请号：US14380312

申请日：2013-02-11

Applicant: SOITEC

Inventor： Richard Ferrant

IPC: H03K17/693 ,  H03K17/00 ,  H03K19/177

CPC classification number: H03K17/693 ,  H03K17/005 ,  H03K17/735 ,  H03K19/17728 ,  H03K2017/6878 ,  H03K2217/0018

Abstract: The present invention relates to a multiplexer comprising at least a first input and a second input and one output connected to the first input via a first pass gate and to the second input via a second pass gate, wherein the first pass gate comprises at least a first double-gate transistor, and the second pass gate comprises at least a second double-gate transistor, and each of the first and second double-gate transistors has a first gate controlled based on a first control signal and a second gate controlled based on a second control signal. The invention further relates to a look-up table and a and an FPGA based on the multiplexer.

Abstract translation: 多路复用器技术领域本发明涉及一种多路复用器，包括至少第一输入端和第二输入端和第一输出端，​​第一输入端和第一输出端经由第一通路栅极连接到第一输入端，并经由第二通路栅极连接到第二输入端， 第一双栅极晶体管，并且第二栅极包括至少第二双栅极晶体管，并且第一和第二双栅极晶体管中的每一个具有基于第一控制信号的第一栅极和基于第一栅极控制的第二栅极 第二控制信号。 本发明还涉及一种基于多路复用器的查找表和FPGA。

公开(公告)号：US20150027519A1

公开(公告)日：2015-01-29

申请号：US14387518

申请日：2013-03-13

Applicant: Soitec

Inventor： Bruno Ghyselen ,  Chantal Arena ,  Frank Dimroth ,  Andreas W. Bett

IPC: H01L31/0725 ,  H01L31/18

CPC classification number: H01L31/0725 ,  C30B29/06 ,  C30B33/06 ,  H01L31/03046 ,  H01L31/0687 ,  H01L31/1844 ,  H01L31/1852 ,  Y02E10/544 ,  Y02P70/521

Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first substrate, providing a second substrate having a lower surface and an upper surface, forming at least one first solar cell layer on the first substrate to obtain a first wafer structure, forming at least one second solar cell layer on the upper surface of the second substrate to obtain a second wafer structure, and bonding the first wafer structure to the second wafer structure, wherein the at least one first solar cell layer is bonded to the lower surface of the second substrate and removing the first substrate.

Abstract translation: 本发明涉及一种用于制造多结太阳能电池器件的方法，包括以下步骤：提供第一衬底，提供具有下表面和上表面的第二衬底，在第一衬底上形成至少一个第一太阳能电池层 以获得第一晶片结构，在所述第二衬底的上表面上形成至少一个第二太阳能电池层以获得第二晶片结构，并将所述第一晶片结构接合到所述第二晶片结构，其中所述至少一个第一太阳能电池 将单元层结合到第二基板的下表面并除去第一基板。

公开(公告)号：US20150022237A1

公开(公告)日：2015-01-22

申请号：US14381098

申请日：2013-02-11

Applicant: Soitec

Inventor： Richard Ferrant

IPC: H03K19/177

CPC classification number: H03K19/17728 ,  H03K19/17764

Abstract: The present invention relates to a look-up table comprising a plurality of register signals (r0-r3); a plurality of inputs signals (A, A′, B, B′); and at least one output signal (Y); and a plurality of pass gates, wherein at least a first pass gate of the plurality of pass gates is controlled by at least a first input signal of the plurality of input signals, and by at least a first register signal, of the plurality of register signals, such that the register signal has priority over the input signal on the operation of the first pass gate.

Abstract translation: 本发明涉及一种包括多个寄存器信号（r0-r3）的查找表; 多个输入信号（A，A'，B，B'）; 和至少一个输出信号（Y）; 以及多个通过门，其中所述多个通过门中的至少第一通过栅极由所述多个输入信号中的至少第一输入信号以及所述多个输入信号中的至少第一寄存器信号来控制 信号，使得寄存器信号在第一通过门的操作上优先于输入信号。

公开(公告)号：US20150001568A1

公开(公告)日：2015-01-01

申请号：US14370903

申请日：2013-01-04

Applicant: Commissariaat a I'energie atomique et aux ene alt ,  SOITEC

Inventor： Yohan Desieres ,  Philippe Gilet ,  Pascal Guenard

IPC: H01L33/22 ,  H01L33/00 ,  G02B5/02 ,  H01L33/10

CPC classification number: H01L33/22 ,  G02B5/0236 ,  G02B5/0284 ,  H01L33/005 ,  H01L33/10 ,  H01L33/32 ,  H01L33/46 ,  H01L2933/0025 ,  H01L2933/0058

Abstract: A device for back-scattering an incident light ray, including: a host substrate; a structured layer; a first face in contact with a front face of the host substrate; a second flat face parallel to the first face; a first material and a second material which form, in a mixed plane, alternating surfaces at least one of whose dimensions is between 300 nm and 800 nm, the mixed plane is between the first and second face of the structured layer; wherein the refractive index of the first and of the second material are different, the structured layer is covered by a specific layer, the specific layer is made of a material which is different from the first and second materials of the structured layer, and the specific layer is crystalline and semi-conductive.

Abstract translation: 一种用于对入射光线进行背散射的装置，包括：主机基板; 结构化层; 与主体基板的前表面接触的第一面; 平行于第一面的第二平面; 第一材料和第二材料，其在混合平面中形成至少一个其尺寸在300nm和800nm之间的交替表面，所述混合平面位于所述结构化层的第一和第二面之间; 其中所述第一和第二材料的折射率不同，所述结构化层被特定层覆盖，所述特定层由与所述结构化层的第一和第二材料不同的材料制成，并且所述特定层 层是晶体和半导电的。

公开(公告)号：US20140346639A1

公开(公告)日：2014-11-27

申请号：US14372659

申请日：2013-01-14

Applicant: Soitec

Inventor： Francois Boedt ,  Roland Brun ,  Olivier Ledoux ,  Eric Butaud

IPC: H01L21/762 ,  H01L29/36 ,  H01L21/66

CPC classification number: H01L21/76254 ,  H01L22/12 ,  H01L22/20 ,  H01L29/36

Abstract: The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor substrate comprising at least one useful silicon layer; inspecting the donor substrate via an inspecting machine in order to detect whether the useful layer contains emerging cavities of a size larger than or equal to a critical size, said critical size being strictly smaller than 44 nm; and manufacturing a semiconductor substrate comprising at least part of the useful layer of the donor substrate if, considering cavities of a size larger than or equal to the critical size, the density or number of cavities in the useful layer of the donor substrate is lower than or equal to a critical defect density or number.

Abstract translation: 本发明涉及一种用于制造半导体衬底的方法，其特征在于，其包括提供包括至少一个有用硅层的至少一个施主半导体衬底; 通过检查机检查供体基板，以便检测有用层是否包含尺寸大于或等于临界尺寸的新出现的空腔，所述临界尺寸严格小于44nm; 以及制造包括供体衬底的有用层的至少一部分的半导体衬底，如果考虑尺寸大于或等于临界尺寸的空腔，则供体衬底的有用层中的空腔的密度或数量低于 或等于临界缺陷密度或数量。

公开(公告)号：US20140299176A1

公开(公告)日：2014-10-09

申请号：US14361149

申请日：2012-12-07

Applicant: SOITEC SOLAR GMBH

Inventor： Eckart Gerster

IPC: H01L31/05

CPC classification number: H01L31/052 ,  H01L31/044 ,  H01L31/048 ,  H01L31/0504 ,  H01L31/0543 ,  H01L31/188 ,  Y02E10/52 ,  Y10T29/49826

Abstract: Apparatus for the industrial wiring and final testing of photovoltaic concentrator modules, consisting of a module frame, a lens disc, a sensor carrier disc and an electrical line routing arrangement, comprising the following features: a) a laser contact-making device for the contactless connection of connecting lines between the individual sensors and of connecting elements and of collective contact plates, wherein the line routing arrangement on the sensor carrier disc as basic structure has in each case 5 CPV sensors connected in parallel, and these parallel circuits are connected in series, b) a device for testing electrical properties, wherein a specific voltage is applied to CPV sensors themselves, and the light emitted by them via the lenses is detected and assessed, c) a device for testing tightness of finished concentrator modules, wherein compressed air is applied to the modules in the interior and the emission of compressed air is checked.

Abstract translation: 用于工业布线和光伏集中器模块的最终测试的装置，包括模块框架，透镜盘，传感器载体盘和电线布线装置，其包括以下特征：a）用于非接触式的激光接触制造装置 各个传感器与连接元件和集体接触板之间的连接线的连接，其中作为基本结构的传感器载体盘上的线路布置在每种情况下都具有并联连接的5个CPV传感器，并且这些并联电路串联连接 b）用于测试电气性能的装置，其中特定电压被施加到CPV传感器本身，并且检测并评估由它们经由透镜发射的光; c）用于测试完成的浓缩器模块的紧密度的装置，其中压缩空气 被应用于内部的模块并检查压缩空气的排放。

公开(公告)号：US20140225182A1

公开(公告)日：2014-08-14

申请号：US14253690

申请日：2014-04-15

Applicant: Soitec

Inventor： Mohamad A. Shaheen ,  Frederic Allibert ,  Gweltaz Gaudin ,  Fabrice Lallement ,  Didier Landru ,  Karine Landry ,  Carlos Mazure

IPC: H01L29/786

CPC classification number: H01L29/78603 ,  H01L29/32 ,  H01L29/7841 ,  H01L31/0248

Abstract: A substrate comprises a base wafer, an insulating layer over the base wafer, and a top semiconductor layer over the insulating layer on a side thereof opposite the base wafer. The insulating layer comprises a charge-confining layer confined on one or both sides with diffusion barrier layers, wherein the charge-confining layer has a density of charges in absolute value higher than 1010 charges/cm2. Alternatively, the insulating layer comprises charge-trapping islands embedded therein, wherein the charge-trapping islands have a total density of charges in absolute value higher than 1010 charges/cm2.

Abstract translation: 衬底包括基底晶片，在基底晶片上方的绝缘层，以及在与基底晶片相对的一侧上的绝缘层上的顶部半导体层。 绝缘层包括限制在具有扩散阻挡层的一侧或两侧的电荷限制层，其中电荷限制层的绝对值的电荷密度高于1010电荷/ cm 2。 或者，绝缘层包括嵌入其中的电荷捕获岛，其中电荷捕获岛具有高于1010电荷/ cm 2的绝对值的电荷的总密度。

公开(公告)号：US08742428B2

公开(公告)日：2014-06-03

申请号：US13659521

申请日：2012-10-24

Applicant: Soitec ,  Christophe Figuet ,  Pierre Tomasini

Inventor： Christophe Figuet ,  Pierre Tomasini

IPC: H01L29/15

CPC classification number: H01L29/205 ,  C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0259 ,  H01L33/04

Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.

Abstract translation: 形成三元III族氮化物材料的方法包括在室中的衬底上的外延生长三元III族氮化物材料。 外延生长包括在室内提供前体气体混合物，其包括氮气前体的分压与腔室中一种或多种III族前体的分压的相对高的比例。 至少部分地由于相对高的比例，可以将三元III族氮化物材料层生长到具有小的V凹坑缺陷的高最终厚度。 使用这种方法制造包括这种三元III族氮化物材料层的半导体结构。

公开(公告)号：US08728913B2

公开(公告)日：2014-05-20

申请号：US13933779

申请日：2013-07-02

Applicant: Soitec

Inventor： Sébastien Kerdiles ,  Walter Schwarzenbach ,  Aziz Alami-Idrissi

IPC: H01L21/30 ,  H01L21/78

CPC classification number: H01L21/30625 ,  H01L21/02032 ,  H01L21/76254

Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions that are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.

Abstract translation: 本发明涉及一种用于将层从施主衬底转移到手柄衬底上的方法，其中，在剥离之后，再次使用剩余的施主衬底。 为了摆脱由于基板的倒角几何形状引起的不期望的突出边缘区域，本发明提出在拆卸发生之前执行附加的蚀刻工艺。