公开(公告)号：US20040262721A1

公开(公告)日：2004-12-30

申请号：US10833883

申请日：2004-04-27

Applicant: STMicroelectronics S.r.I.

Inventor： Claudio Deodato ,  Roberto Tiziani

IPC: H01L021/48 ,  H01L023/495

CPC classification number: H01L21/4842 ,  H01L23/49551 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A planar metallic foil is formed defining a lie plane which includes a supporting frame for a mount pad and corresponding leads being short-circuited to the mount pad. The mount pad is then down-set on a plane being parallel to the lie plane so as to keep at least a group of leads on the lie plane and separate by shearing the mount plane from the group of leads. A die is then mounted on a first surface of the mount pad. Electrical connections are then formed between the die and the group of leads. The frame is then encapsulated in a protective package so as to leave a second surface of the mount pad, being opposite to the first surface, exposed from the protective package.

Abstract translation: 形成平面金属箔，限定了一个平面，其包括用于安装垫的支撑框架，并且相应的引线被短路到安装垫。 然后将安装焊盘放置在平行于平面的平面上，以便在平面上保持至少一组引线，并通过将安装平面与引线组剪切分离。 然后将模具安装在安装垫的第一表面上。 然后在管芯和导线组之间形成电连接。 然后将框架封装在保护性封装中，以便从安全衬垫的第二表面离开第一表面，露出自保护封装。

公开(公告)号：US20040255920A1

公开(公告)日：2004-12-23

申请号：US10814819

申请日：2004-03-31

Applicant: STMicroelectronics S.r.I.

Inventor： Giovanni L. Torrisi ,  Antonino Torres ,  Nicola A. Liporace

IPC: F02P007/03

CPC classification number: F02P7/035 ,  F02D2041/2051 ,  F02D2041/2075 ,  F02D2041/2082 ,  F02P3/0442 ,  F02P15/08 ,  F02P17/12 ,  F02P2017/121

Abstract: A control circuit is connected to a plurality of driving stages. Each driving stage includes a high-voltage terminal for driving an inductive load. The control circuit is provided with a corresponding plurality of control stages. These control stages are integrated in a single semiconductor body and connected each to the high-voltage terminal of a respective driving stage.

Abstract translation: 控制电路连接到多个驱动级。 每个驱动级包括用于驱动感性负载的高压端子。 控制电路设有相应的多个控制级。 这些控制级集成在单个半导体本体中，并分别连接到相应的驱动级的高电压端子。

公开(公告)号：US20040217447A1

公开(公告)日：2004-11-04

申请号：US10726264

申请日：2003-12-02

Applicant: STMicroelectronics, S.r.I

Inventor： Alessio M. D'arrigo Guiseppe ,  Rosario C. Spinella ,  Guiseppe Arena ,  Simona Lorenti

IPC: H01L029/00

CPC classification number: B81C1/00507 ,  G01N27/447 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764

Abstract: A process is presented for realizing buried microchannels (10) in an integrated structure (1) comprising a monocrystalline silicon substrate (2). The process forms in the substrate (2) at least one trench (4). A microchannel (10) is obtained starting from a small surface port of the trench (4) by anisotropic etching of the trench. The microchannel (10) is then completely buried in the substrate (2) by growing a microcrystalline structure to enclose the small surface port.

Abstract translation: 提出了在包括单晶硅衬底（2）的集成结构（1）中实现埋入微通道（10）的过程。 该工艺在衬底（2）中形成至少一个沟槽（4）。 通过沟槽的各向异性蚀刻从沟槽（4）的小表面端口开始获得微通道（10）。 然后通过生长微晶结构以包围小表面端口将微通道（10）完全掩埋在衬底（2）中。

公开(公告)号：US20040171397A1

公开(公告)日：2004-09-02

申请号：US10754465

申请日：2004-01-09

Applicant: STMicroelectronics N.V. ,  STMicroelectronics S.r.I.

Inventor： Patrick Cerisier ,  Giovanni Cerusa

IPC: H04B015/00

CPC classification number: H03F3/211 ,  H03F3/2175 ,  H03F2200/331 ,  H03F2200/372

Abstract: A power amplification device includes an input for receiving a signal having a useful or desired frequency band, and power amplification circuitry of the delta-sigma type connected to the input. The power amplification circuitry exhibits an order greater than or equal to one in the useful frequency band, and an order greater than or equal to one outside the useful frequency band.

Abstract translation: 功率放大装置包括用于接收具有有用或期望频带的信号的输入端和连接到输入端的Δ-Σ型功率放大电路。 功率放大电路在有用频带中呈现大于或等于1的阶数，以及在有用频带外的大于或等于1的阶数。

公开(公告)号：US20040165434A1

公开(公告)日：2004-08-26

申请号：US10739928

申请日：2003-12-18

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Mastroianni ,  Massimiliano Scotti ,  Antonio Geraci ,  Andrea Pozzato

IPC: G11C011/34

CPC classification number: G11C16/10 ,  G11C2216/14

Abstract: A non-volatile memory device suitable to be programmed in a sequential mode. The device includes a plurality of blocks of memory cells each one for storing a word, each block being identified by an address. An input circuit for loading an input address at the beginning of a programming procedure and an internal circuit for setting an internal address to the input address. The device further includes a data input circuit for loading a predetermined number of input words in succession, and a latch circuit for latching a page consisting of the predetermined number of input words. The memory then executes a programming operation including writing the page in the blocks identified by consecutive addresses starting from the internal address, and increments the internal address of the predetermined number in response to the completion of the programming operation.

Abstract translation: 适用于以顺序模式编程的非易失性存储器件。 该装置包括多个存储单元块，每个存储单元块用于存储单词，每个块由地址标识。 用于在编程程序开始时加载输入地址的输入电路和用于将内部地址设置为输入地址的内部电路。 该装置还包括用于连续加载预定数量的输入字的数据输入电路和用于锁存由预定数量的输入字构成的页的锁存电路。 然后，存储器执行编程操作，包括在从内部地址开始的连续地址识别的块中写入页面，并且响应于编程操作的完成来增加预定数量的内部地址。

公开(公告)号：US20040130948A1

公开(公告)日：2004-07-08

申请号：US10742181

申请日：2003-12-19

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Rolandi

IPC: G11C016/04 ,  G11C011/34

CPC classification number: G11C16/08 ,  G11C8/10

Abstract: A nonvolatile memory with a memory array arranged in rows and columns of memory cells in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.

公开(公告)号：US20040125007A1

公开(公告)日：2004-07-01

申请号：US10713541

申请日：2003-11-14

Applicant: STMicroelectronics S.r.I.

Inventor： Saverio Pezzini

IPC: H03M001/12

CPC classification number: H03M1/1076 ,  H03M1/12

Abstract: An integrated circuit includes an input pad for receiving an externally generated analog signal, and a pre-sampling circuit for pre-sampling at least one internally generated analog reference signal. An analog-to-digital converter is connected to the input pad for providing a numerical value of the externally generated analog signal, and is connected to the pre-sampling circuit for providing a numerical value of the internally generated analog reference signal. A fault signaling circuit is connected to the pre-sampling circuit and to the analog-to-digital converter for generating a fault signal when the numerical value of the externally generated analog signal is equal to the numerical value of the internally generated analog reference signal. The fault signal indicates that an electrical connection providing the externally generated analog signal to the input pad is faulty.

Abstract translation: 集成电路包括用于接收外部产生的模拟信号的输入焊盘和用于对至少一个内部产生的模拟参考信号进行预采样的预采样电路。 模拟 - 数字转换器连接到输入焊盘，用于提供外部产生的模拟信号的数值，并连接到预采样电路，以提供内部产生的模拟参考信号的数值。 当外部产生的模拟信号的数值等于内部产生的模拟参考信号的数值时，故障信号电路连接到预采样电路和模拟 - 数字转换器，用于产生故障信号。 故障信号表示向输入焊盘提供外部产生的模拟信号的电气连接有故障。

公开(公告)号：US20040112652A1

公开(公告)日：2004-06-17

申请号：US10696723

申请日：2003-10-29

Applicant: STMicroelectronics S.r.I.

Inventor： Giuseppe Esposito Corcione ,  Gianguido Rizzotto ,  Gianluca Vitale

IPC: B60K001/00

CPC classification number: B60W10/10 ,  B60K6/46 ,  B60K6/48 ,  B60L2240/486 ,  B60W2510/244 ,  B60W2710/105 ,  Y02T10/52 ,  Y02T10/6217 ,  Y02T10/6221

Abstract: A parallel configuration system for hybrid propulsion vehicles is provided. The drive thrust is distributed between an electric engine and an internal combustion engine through a transmission system delivering the torque of both engines to the vehicle wheels. The internal combustion engine is a diesel engine operating at steady state at an operation point having the highest efficiency and with the consumption and emissions being reduced.

Abstract translation: 提供了一种用于混合推进车辆的并联配置系统。 驱动推力通过传递系统分布在电动发动机和内燃机之间，传动系统将两个发动机的扭矩传递给车轮。 内燃机是在操作点处于稳定状态的柴油发动机，效率最高，消耗和排放减少。

公开(公告)号：US20040072396A1

公开(公告)日：2004-04-15

申请号：US10449749

申请日：2003-05-29

Applicant: STMicroelectronics S.r.I.

Inventor： Roberto Tiziani ,  Loic Renard ,  Battista Vitali

IPC: H01L021/8238

CPC classification number: H01L24/85 ,  H01L23/4952 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05073 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20757 ,  H01L2924/2076 ,  H01L2924/351 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor electronic device is disclosed, which includes a die of a semiconductor material and a holder connected electrically together by wire leads of copper, the semiconductor material die being formed with a plurality of contact pads; the device being characterized by having a welding stud bump of a metal material selected from a group comprising gold, palladium, and alloys thereof, formed on each contact pad in said plurality, each copper wire lead being welded with one end on a stud bump and with the other end to said holder. This electronic device is highly reliable and can be fabricated simply at a low cost.

Abstract translation: 公开了一种半导体电子器件，其包括半导体材料的裸片和由铜的引线电连接的保持器，所述半导体材料管芯形成有多个接触焊盘; 该装置的特征在于具有形成在所述多个中的每个接触焊盘上的金，钯及其合金的金属材料的焊接凸块，每个铜线引线一端焊接在螺柱凸块上， 另一端到所述支架。 该电子装置是高度可靠的，并且可以以低成本简单地制造。

公开(公告)号：US20040037357A1

公开(公告)日：2004-02-26

申请号：US10459104

申请日：2003-06-10

Applicant: STMicroelectronics S.r.I.

Inventor： Daniele Bagni ,  Flavio Benussi ,  Bruno Biffi

IPC: H04N007/12

CPC classification number: G06T9/005 ,  G06T9/007 ,  H04N19/124 ,  H04N19/149 ,  H04N19/15 ,  H04N19/152 ,  H04N19/159 ,  H04N19/172 ,  H04N19/61

Abstract: A method for controlling the bit-rate of a bitstream of encoded video signals at a variable bitrate, the bitstream being generated by compressing a video sequence of moving pictures, wherein each picture comprises a plurality of macroblocks of pixels compressed by any of transform coding, temporal prediction, bi-dimensional motion compensated interpolation or combinations thereof, to produce any of I and/or P and/or B frames, the method involving quantization of said macroblocks effected as a function of a quantization parameter. The method includes defining a target bit-rate as well as maximum positive and negative error values between the target bit-rate and an average value of the current bit-rate of the bitstream, controlling the current bit-rate in order to constrain it between said maximum positive and negative error values, and defining an allowed range of variation for updating at least one reference parameter representative of the average value of the quantization parameter over each picture, wherein said allowed range is determined as a function of the target bit-rate and the maximum positive and negative error values.

Abstract translation: 一种用于以可变比特率控制编码视频信号的比特流的比特率的方法，所述比特流是通过压缩运动图像的视频序列而产生的，其中每个图像包括通过任何变换编码压缩的多个像素宏块， 时间预测，双维运动补偿内插或其组合，以产生I和/或P和/或B帧中的任一个，所述方法涉及作为量化参数的函数而影响所述宏块的量化。 该方法包括在目标比特率和比特流的当前比特率的平均值之间定义目标比特率以及最大正和负误差值，控制当前比特率以便将其限制在 所述最大正和负误差值，并且定义允许的变化范围，用于更新表示每个图像上的量化参数的平均值的至少一个参考参数，其中所述允许范围被确定为目标比特率的函数 和最大正负误差值。