公开(公告)号：US10014389B2

公开(公告)日：2018-07-03

申请号：US15219403

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/3086 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

Abstract: One illustrative method disclosed herein includes, among other things, forming channel semiconductor material for a nano-sheet device and a transistor device, forming a device gate insulation layer on both the nano-sheet device and on the transistor device, and forming first and second sacrificial gate structures for the nano-sheet device and the transistor device. In this example, the method also includes removing the sacrificial gate structures so as to define, respectively, first and second gate cavities, wherein the device gate insulation layer is exposed within each of the gate cavities, removing the device gate insulation layer for the transistor device from within the first gate cavity while leaving the device gate insulation layer in position within the second gate cavity, and forming first and second replacement gate structures in the first and second gate cavities, respectively.

公开(公告)号：US20180166319A1

公开(公告)日：2018-06-14

申请号：US15376831

申请日：2016-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/7682 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

公开(公告)号：US20180122702A1

公开(公告)日：2018-05-03

申请号：US15846365

申请日：2017-12-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/49 ,  H01L27/088 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L21/82345 ,  H01L21/02181 ,  H01L21/28088 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A device includes a first transistor device having a first threshold voltage and including a first gate electrode structure positioned in a first gate cavity. The first gate electrode structure includes a first gate insulation layer, a first barrier layer, a first work function material layer formed above the first barrier layer, a second barrier layer formed above the first work function material layer, and a first conductive material formed above the second barrier layer. A second transistor device has a second threshold voltage different than the first threshold voltage and includes a second gate electrode structure positioned in a second cavity defined in the dielectric layer. The second gate electrode structure includes a second gate insulation layer, a second work function material layer, the second barrier layer formed above the second work function material layer, and a second conductive material formed above the second barrier layer.

公开(公告)号：US20170278844A1

公开(公告)日：2017-09-28

申请号：US15082242

申请日：2016-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC: H01L27/088 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US20170243790A1

公开(公告)日：2017-08-24

申请号：US15050540

申请日：2016-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Catherine B. Labelle ,  Chanro Park ,  Hoon Kim

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3105

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545

Abstract: A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is formed above the plurality of fins and the plurality of gate structures. The first mask layer has at least one fin cut opening and at least one gate cut opening defined therein. A first portion of a first fin of the plurality of fins disposed below the fin cut opening is removed to define a fin cut cavity. A second portion of a first gate structure of the plurality of gate structures disposed below the gate cut opening is removed to define a gate cut cavity. An insulating material layer is concurrently formed in at least a portion of the fin cut cavity and the gate cut cavity.

公开(公告)号：US09653356B2

公开(公告)日：2017-05-16

申请号：US14822340

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/768 ,  H01L21/02 ,  H01L27/088 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2221/1026 ,  H01L2221/1036

Abstract: One illustrative method disclosed includes, among other things, forming a silicon dioxide etch stop layer on and in contact with a source/drain region and adjacent silicon nitride sidewall spacers positioned on two laterally spaced-apart transistors having silicon dioxide gate cap layers, performing a first etching process through an opening in a layer of insulating material to remove the silicon nitride material positioned above the source/drain region, performing a second etching process to remove a portion of the silicon dioxide etch stop layer and thereby expose a portion of the source/drain region, and forming a conductive self-aligned contact that is conductively coupled to the source/drain region.

公开(公告)号：US09646884B2

公开(公告)日：2017-05-09

申请号：US14699122

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Sukwon Hong ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/28

CPC classification number: H01L21/823431 ,  H01L21/28088 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823481

Abstract: The present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a recess in the dielectric layer on each side of each fin, each recess being for a metal gate; forming sidewall spacers on each side of each recess; depositing a high-k dielectric liner in each recess and on a top surface of each of the fins; depositing a metal liner over the high-k dielectric layer; depositing a non-conformal organic layer (NCOL) over a top surface of the dielectric layer to pinch-off a top of each recess; depositing an OPL and ARC over the NCOL; etching the OPL, ARC and NCOL over a portion of the dielectric layer and recesses in a first region; and etching the portion of the recesses to remove residual NCOL present at a bottom of each recess of the portion of the recesses.

公开(公告)号：US20170110549A1

公开(公告)日：2017-04-20

申请号：US14887927

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/417 ,  H01L27/02 ,  H01L29/06 ,  H01L27/088 ,  H01L29/45 ,  H01L29/08

CPC classification number: H01L29/41775 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes a stepped conductive source/drain structure with a cavity defined therein, the cavity being located vertically above an active region, a non-conductive structure positioned in the cavity, a layer of insulating material positioned above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, a gate contact opening defined in the layer of insulating material and a conductive gate contact positioned in the gate contact opening that is conductively coupled to the gate structure, wherein at least a portion of the conductive gate contact is positioned vertically above the non-conductive structure.

公开(公告)号：US09601387B2

公开(公告)日：2017-03-21

申请号：US14147108

申请日：2014-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Harry Cai ,  Chanro Park ,  Hoon Kim

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823828 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/66545

Abstract: Methods of forming a PFET dielectric cap with varying concentrations of H2 reactive gas and the resulting devices are disclosed. Embodiments include forming p-type and n-type metal gate stacks, each surrounded by SiN spacers; forming an ILD surrounding the SiN spacers; planarizing the ILD, the metal gate stacks, and the SiN spacers; determining at least one desired threshold voltage for the p-type metal gate stack; forming a first cavity in the p-type metal gate stack for each desired threshold voltage and a second cavity in the n-type metal gate stack; selecting a first nitride layer for each first cavity, the first nitride layer for each cavity having a concentration of hydrogen reactive gas based on the desired threshold voltage associated with the cavity; forming the first nitride layers in the respective first cavities; and forming a second nitride layer, with a hydrogen rich reactive gas, in the second cavity.

公开(公告)号：US20170040220A1

公开(公告)日：2017-02-09

申请号：US14820701

申请日：2015-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L29/49 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L21/82345 ,  H01L21/02181 ,  H01L21/28088 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method includes forming first and second gate cavities so as to expose first and second portions of a semiconductor material. A gate insulation layer is formed in the first and second gate cavities. A first work function material layer is formed in the first gate cavity. A second work function material layer is formed in the second gate cavity. A first barrier layer is selectively formed above the first work function material layer and the gate insulation layer in the first gate cavity. A second barrier layer is formed above the first barrier layer in the first gate cavity and above the second work function material layer and the gate insulation layer in the second gate cavity. A conductive material is formed above the second barrier layer in the first and second gate cavities in the presence of a treatment species to define first and second gate electrode structures.

Abstract translation: 一种方法包括形成第一和第二栅极腔以暴露半导体材料的第一和第二部分。 栅极绝缘层形成在第一和第二栅极腔中。 第一工作功能材料层形成在第一浇口腔中。 第二工作功能材料层形成在第二浇口腔中。 第一栅极层选择性地形成在第一栅极腔上的第一功函数材料层和栅极绝缘层之上。 第二势垒层形成在第一栅极腔中的第一势垒层上方，并且在第二栅极腔中的第二功函数材料层和栅极绝缘层之上。 在存在处理物质的情况下，在第一和第二栅极腔中的第二阻挡层上方形成导电材料，以限定第一和第二栅电极结构。