公开(公告)号：US10090051B2

公开(公告)日：2018-10-02

申请号：US15686416

申请日：2017-08-25

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/24 ,  G11C5/02 ,  G11C16/04 ,  G11C11/56

Abstract: Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.

公开(公告)号：US20180137922A1

公开(公告)日：2018-05-17

申请号：US15350229

申请日：2016-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/32 ,  G11C16/14

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/20 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.

公开(公告)号：US09842652B2

公开(公告)日：2017-12-12

申请号：US14961042

申请日：2015-12-07

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/24 ,  G11C5/05 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26

Abstract: Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.

公开(公告)号：US20170294383A1

公开(公告)日：2017-10-12

申请号：US15095401

申请日：2016-04-11

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

公开(公告)号：US09778846B2

公开(公告)日：2017-10-03

申请号：US15244163

申请日：2016-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G06F12/14 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/14 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1052 ,  G06F2212/214 ,  G06F2212/2532 ,  Y02D10/14

Abstract: Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

公开(公告)号：US20170278572A1

公开(公告)日：2017-09-28

申请号：US15615652

申请日：2017-06-06

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/08 ,  G11C5/02 ,  G11C16/04 ,  G11C8/10

CPC classification number: G11C16/08 ,  G11C5/02 ,  G11C5/025 ,  G11C8/10 ,  G11C16/0483

Abstract: Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.

公开(公告)号：US09773553B1

公开(公告)日：2017-09-26

申请号：US15241740

申请日：2016-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Han Zhao

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of the plurality of strings is selectively connected to a common data line through a corresponding respective first select gate and selectively connected to a common source through a corresponding respective second select gate. A first access line is coupled to a respective memory cell of a first position of each string of the plurality of strings. A second access line is coupled to a respective memory cell of a second position of each string of a first subset of the plurality of strings, and a third access line is coupled to a respective memory cell of the second position of each string of a second subset of the plurality of strings.

公开(公告)号：US09747991B2

公开(公告)日：2017-08-29

申请号：US14997278

申请日：2016-01-15

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/12 ,  G11C7/00 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C7/00 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

Abstract: Embodiments are provided that include a method including providing a first voltage to a memory cell prior to an operation, wherein a magnitude of the first voltage is approximately 5 volts. The method further includes providing a second voltage to the memory cell during the operation, wherein a magnitude of the second voltage is in the range of approximately 1.0 and 1.5 volts. The method also includes determining a state of the memory cell after providing the first voltage and the second voltage.

公开(公告)号：US09711514B2

公开(公告)日：2017-07-18

申请号：US15043921

申请日：2016-02-15

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  H01L27/11556 ,  H01L21/04 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L27/11556 ,  G11C16/04 ,  G11C16/0408 ,  H01L21/04 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/04 ,  H01L29/16

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US09697907B2

公开(公告)日：2017-07-04

申请号：US15227623

申请日：2016-08-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Aaron Yip

IPC: G11C16/04 ,  G11C16/28 ,  G11C7/02 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/28 ,  G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3427

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.