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    Flash memory system using complementary voltage supplies
    112.
    发明授权
    Flash memory system using complementary voltage supplies 有权
    闪存系统使用互补电源

    公开(公告)号：US09508443B2

    公开(公告)日：2016-11-29

    申请号：US15135346

    申请日：2016-04-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC: G11C16/06 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

    CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C8/08 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/04 ,  H01L27/11521

    Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

    Abstract translation: 非易失性存储器件包括第一导电类型的半导体衬底。 非易失性存储单元的阵列位于半导体衬底中并且被布置成多个行和列。 每个存储单元包括第二导电类型的半导体衬底的表面上的第一区域和第二导电类型的半导体衬底的表面上的第二区域。 沟道区域在第一区域和第二区域之间。 字线覆盖在沟道区域的第一部分上，并且与第一区域绝缘，并且与第一区域相邻并且与第一区域几乎没有或没有重叠。 浮动栅极覆盖沟道区域的第二部分，与第一部分相邻，并与第二部分绝缘并与第二区域相邻。 耦合栅极覆盖浮栅。 位线连接到第一区域。 在程序，读取或擦除的操作期间，负电压可以被施加到所选择的或未选择的存储单元的字线和/或耦合门。

    Non-volatile memory array and method of using same for fractional word programming
    115.
    发明授权
    Non-volatile memory array and method of using same for fractional word programming 有权
    非易失性存储器阵列及其分数字编程的使用方法

    公开(公告)号：US09123401B2

    公开(公告)日：2015-09-01

    申请号：US13652447

    申请日：2012-10-15

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC: G11C5/14 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C8/08

    CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10

    Abstract: A non-volatile memory device that includes N planes of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns. Each of the N planes includes gate lines that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor.

    Abstract translation: 包括非易失性存储器单元的N个平面（其中N是大于1的整数）的非易失性存储器件。 非易失性存储单元的每个平面包括以行和列配置的多个存储器单元。 N平面中的每一个包括在其中存储单元的行延伸但不延伸到非易失性存储单元的N个平面中的其他平面的栅极线。 控制器被配置为将多个数据字中的每一个分成N个小数字，并且将每个数据字的N个分数字中的每一个分解成非易失性存储单元的N个平面中的不同的一个。 控制器使用编程电流和编程时间段进行编程，并且可以配置为通过一个因素改变编程电流，并根据因子反向改变程序时间段。

    Read and programming decoding system for analog neural memory
    117.
    发明授权
    Read and programming decoding system for analog neural memory 有权

    公开(公告)号：US12237011B2

    公开(公告)日：2025-02-25

    申请号：US17853315

    申请日：2022-06-29

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Han Tran ,  Kha Nguyen ,  Hien Pham

    IPC: G11C11/56 ,  G06F17/16 ,  G06N3/06 ,  G11C11/16 ,  G11C11/4074

    Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.

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