公开(公告)号：US20160218172A1

公开(公告)日：2016-07-28

申请号：US14606265

申请日：2015-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Pei Hsieh ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC: H01L49/02 ,  H01L21/311

CPC classification number: H01L28/90

Abstract: The present disclosure relates a metal-insulator-metal (MIM) capacitor. In some embodiments, the MIM capacitor has a capacitor bottom metal (CBM) electrode arranged over a semiconductor substrate. The MIM capacitor has a high-k dielectric disposed over the CBM electrode and a capacitor top metal (CTM) electrode arranged over the high-k dielectric layer. The MIM capacitor has a dummy structure that is disposed vertically over the high-k dielectric layer and laterally apart from the CTM electrode. The dummy structure includes a conductive body having a same material as the CTM electrode.

Abstract translation: 本发明涉及金属 - 绝缘体 - 金属（MIM）电容器。 在一些实施例中，MIM电容器具有布置在半导体衬底上的电容器底部金属（CBM）电极。 MIM电容器具有布置在CBM电极上的高k电介质和布置在高k电介质层上的电容器顶金属（CTM）电极。 MIM电容器具有垂直设置在高k电介质层上并与CTM电极横向分开的虚拟结构。 虚设结构包括具有与CTM电极相同的材料的导电体。

公开(公告)号：US20160204118A1

公开(公告)日：2016-07-14

申请号：US14596340

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yung-Chang Chang

IPC: H01L27/115 ,  H01L29/423 ,  H01L23/528 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/265 ,  H01L21/768 ,  H01L29/788 ,  H01L23/532

CPC classification number: H01L27/11521 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is arranged laterally between the first and second individual S/D regions, and is separated from the first individual S/D region by a first channel region and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D. A floating gate is disposed over the first channel region and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A wordline is disposed over the first channel region and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the wordline is a concave surface.

Abstract translation: 本公开的一些实施例涉及闪存设备。 闪存器件包括在半导体衬底内间隔开的第一和第二个源/漏（S / D）区域。 公共S / D区域横向地布置在第一和第二单独S / D区域之间，并且通过第一沟道区域与第一单独S / D区域分离，并且与第二个别S / D区域分开第二个 渠道区域。 擦除门被布置在公共S / D上。 浮置栅极设置在第一沟道区上方并且布置在擦除栅极的第一侧。 控制栅极设置在浮动栅极上。 字线布置在第一通道区域上方，并通过浮动栅极和控制栅极与擦除栅极间隔开。 字线的上表面是凹面。

公开(公告)号：US20160087056A1

公开(公告)日：2016-03-24

申请号：US14493538

申请日：2014-09-23

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Chang-Ming Wu ,  Tsung-Hsueh Yang ,  Sheng-Chieh Chen ,  Shih-Chang Liu

IPC: H01L29/423 ,  H01L27/115 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/788 ,  H01L29/7881

Abstract: Some embodiments relate to a memory device with an asymmetric floating gate geometry. A control gate is arranged over a floating gate. An erase gate is arranged laterally adjacent the floating gate, and is separated from the floating gate by a tunneling dielectric layer. A sidewall spacer is arranged along a vertical sidewall of the control gate, and over an upper surface of the floating gate. A portion of the floating gate upper surface forms a “ledge,” or a sharp corner, which extends horizontally past the sidewall spacer. A sidewall of the floating gate forms a concave surface, which tapers down from the ledge towards a neck region within the floating gate. The ledge provides a faster path for tunneling of the electrons through the tunneling dielectric layer compared to a floating gate with a planar sidewall surface. The ledge consequently improves the erase speed of the memory device.

Abstract translation: 一些实施例涉及具有不对称浮动门几何形状的存储器件。 控制门布置在浮动门上。 擦除栅极横向布置在浮动栅极附近，并且通过隧道电介质层与浮动栅极分离。 侧壁间隔件沿着控制栅极的垂直侧壁并且在浮动栅极的上表面上方布置。 浮动门上表面的一部分形成水平延伸通过侧壁间隔物的“凸缘”或尖角。 浮动栅极的侧壁形成凹入表面，其从凸缘向下朝向浮动门内的颈部区域逐渐变细。 与具有平面侧壁表面的浮动栅极相比，该凸缘提供了更快的隧道隧道隧穿隧道介电层的路径。 因此，该凸起因此提高了存储器件的擦除速度。

公开(公告)号：US20160064656A1

公开(公告)日：2016-03-03

申请号：US14471082

申请日：2014-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-ken Lin ,  Chang-Ming Wu ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/1675

Abstract: A phase change memory (PCM) cell with a heating element electrically isolated from laterally surrounding regions of the PCM cell by a cavity is provided. A dielectric region is arranged between first and second conductors. A heating plug is arranged within a hole extending through the dielectric region to the first conductor. The heating plug includes a heating element running along sidewalls of the hole, and includes a sidewall structure including a cavity arranged between the heating element and the sidewalls. A phase change element is in thermal communication with the heating plug and arranged between the heating plug and the second conductor. Also provide is a method for manufacturing the PCM cell.

Abstract translation: 提供了具有通过空腔与PCM单元的横向周围区域电隔离的加热元件的相变存储器（PCM）单元。 电介质区域布置在第一和第二导体之间。 在穿过介电区延伸到第一导体的孔内布置加热塞。 加热插头包括沿着孔的侧壁延伸的加热元件，并且包括侧壁结构，该侧壁结构包括布置在加热元件和侧壁之间的空腔。 相变元件与加热塞热连通并且布置在加热塞和第二导体之间。 还提供了用于制造PCM单元的方法。

公开(公告)号：US09257498B1

公开(公告)日：2016-02-09

申请号：US14450532

申请日：2014-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chern-Yow Hsu ,  Shih-Chang Liu ,  Ching-Sheng Chu ,  Chia-Shiung Tsai

IPC: H01L27/108 ,  H01L29/94 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/283 ,  H01L21/321

CPC classification number: H01L28/60 ,  H01L21/283 ,  H01L21/321 ,  H01L21/32133 ,  H01L28/90

Abstract: Some embodiments relate to a metal-insulator-metal (MIM) capacitor, which includes a capacitor a capacitor bottom metal (CBM) electrode, a high k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high k dielectric layer. In some embodiments, the MIM capacitor comprises CTM protective sidewall regions, which extend along vertical sidewall surfaces of the CTM electrode, and protect the CTM electrode from leakage, premature voltage breakdown, or burn out, due to metallic residue or etch damage formed on the sidewalls during one or more etch process(es) used to form the CTM electrode. In some embodiments, the MIM capacitor comprises CBM protective sidewall regions, which extend along vertical sidewall surfaces of the CBM electrode. In some embodiments, the MIM capacitor comprises both CBM and CTM protective sidewall regions.

Abstract translation: 一些实施例涉及金属 - 绝缘体金属（MIM）电容器，其包括电容器底部电容（CBM）电极，布置在CBM电极上的高k电介质层和布置在电容器顶部金属（CTM）电极上的电容器顶部金属（CTM）电极） 高k电介质层。 在一些实施例中，MIM电容器包括沿着CTM电极的垂直侧壁表面延伸的CTM保护侧壁区域，并且由于金属残留物或蚀刻损伤上形成的金属残留物或蚀刻损伤而保护CTM电极免受泄漏，过早的电压击穿或烧坏 在用于形成CTM电极的一个或多个蚀刻工艺期间的侧壁。 在一些实施例中，MIM电容器包括沿着CBM电极的垂直侧壁表面延伸的CBM保护侧壁区域。 在一些实施例中，MIM电容器包括CBM和CTM保护侧壁区域。

公开(公告)号：US20160035817A1

公开(公告)日：2016-02-04

申请号：US14450532

申请日：2014-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chern-Yow Hsu ,  Shih-Chang Liu ,  Ching-Sheng Chu ,  Chia-Shiung Tsai

IPC: H01L49/02 ,  H01L21/283 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L28/60 ,  H01L21/283 ,  H01L21/321 ,  H01L21/32133 ,  H01L28/90

Abstract: Some embodiments relate to a metal-insulator-metal (MIM) capacitor, which includes a capacitor a capacitor bottom metal (CBM) electrode, a high k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high k dielectric layer. In some embodiments, the MIM capacitor comprises CTM protective sidewall regions, which extend along vertical sidewall surfaces of the CTM electrode, and protect the CTM electrode from leakage, premature voltage breakdown, or burn out, due to metallic residue or etch damage formed on the sidewalls during one or more etch process(es) used to form the CTM electrode. In some embodiments, the MIM capacitor comprises CBM protective sidewall regions, which extend along vertical sidewall surfaces of the CBM electrode. In some embodiments, the MIM capacitor comprises both CBM and CTM protective sidewall regions.

Abstract translation: 一些实施例涉及金属 - 绝缘体金属（MIM）电容器，其包括电容器底部电容（CBM）电极，布置在CBM电极上的高k电介质层和布置在电容器顶部金属（CTM）电极上的电容器顶部金属（CTM）电极） 高k电介质层。 在一些实施例中，MIM电容器包括沿着CTM电极的垂直侧壁表面延伸的CTM保护侧壁区域，并且由于金属残留物或蚀刻损伤上形成的金属残留物或蚀刻损伤而保护CTM电极免受泄漏，过早的电压击穿或烧坏 在用于形成CTM电极的一个或多个蚀刻工艺期间的侧壁。 在一些实施例中，MIM电容器包括沿着CBM电极的垂直侧壁表面延伸的CBM保护侧壁区域。 在一些实施例中，MIM电容器包括CBM和CTM保护侧壁区域。

公开(公告)号：US20150380568A1

公开(公告)日：2015-12-31

申请号：US14316864

申请日：2014-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of manufacturing a semiconductor structure of a pair of split gate flash memory cells is provided. A pair of select gates spaced on a semiconductor substrate is formed, and a sacrificial spacer filling a central region between the select gates is formed. A charge trapping dielectric layer is formed conformally along sidewalls of the select gates and over top surfaces of the sacrificial spacer and the select gates, and a pair of memory gates corresponding to the pair of select gates is formed over and laterally abutting the charge trapping dielectric layer. The resulting semiconductor structure is also provided.

Abstract translation: 提供了一对制造分离栅闪存单元的半导体结构的方法。 形成在半导体衬底上间隔开的一对选择栅极，并且形成填充选择栅极之间的中心区域的牺牲隔离物。 电荷捕获电介质层沿着选择栅极的侧壁和牺牲间隔物和选择栅极的顶表面保形地形成，并且对应于该对选择栅极的一对存储栅极形成在电荷捕获电介质上方并横向邻接 层。 还提供所得的半导体结构。

公开(公告)号：US20150372136A1

公开(公告)日：2015-12-24

申请号：US14310277

申请日：2014-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7831 ,  H01L29/792

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括包括第一源极/漏极区域和第二源极/漏极区域的半导体衬底。 第一和第二源极/漏极区域之间形成沟道区域。 半导体结构还包括选择栅极和在沟道区域上的第一和第二源极/漏极区域间隔开的存储栅极。 选择栅极延伸在沟道区上方并且终止于具有沿着沿着选择栅极的长度延伸的轴线的不对称的顶表面的线端，并且平分选择栅极的宽度。 更重要的是，半导体结构包括布置在存储器栅极和选择栅极的相邻侧壁之间并且布置在存储器栅极下方的电荷捕获电介质。 还提供了制造半导体结构的方法。

公开(公告)号：US20150372121A1

公开(公告)日：2015-12-24

申请号：US14308872

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Chen ,  Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/7883

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided.

Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括具有源极区和漏极区的半导体衬底。 此外，半导体结构包括在源极和漏极区域之间间隔开半导体衬底的浮置栅极，字线和擦除栅极，其中浮置栅极布置在字线和擦除栅极之间。 半导体结构还包括设置在字线和浮置栅极之间的第一电介质侧壁区域以及设置在擦除栅极和浮置栅极之间的第二电介质侧壁区域。 第一电介质侧壁区域的厚度大于第二电介质侧壁区域的厚度。 还提供了制造半导体结构的方法和包括半导体结构的集成电路。

公开(公告)号：US09196825B2

公开(公告)日：2015-11-24

申请号：US14016343

申请日：2013-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hang Huang ,  Fu-Ting Sung ,  Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L29/66 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

Abstract translation: 集成电路器件包括衬底和磁隧道结（MTJ）。 MTJ至少包括被钉扎层，阻挡层和自由层。 MTJ形成在衬底的表面上。 在被钉扎层，阻挡层和自由层中，自由层首先形成并且最接近表面。 这使得在蚀刻自由层之前，可以在自由层的周边区域上形成间隔物。 由蚀刻或其它自由层边界限定工艺导致的对自由层的任何损伤通过间隔物保持与隧道结一定距离。