公开(公告)号：US20170110202A1

公开(公告)日：2017-04-20

申请号：US14883791

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: G11C29/02 ,  H01L23/528 ,  H01L29/51 ,  G01R31/26 ,  H01L27/115 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/544 ,  H01L29/49

CPC classification number: G01R31/2644 ,  H01L21/32133 ,  H01L21/76877 ,  H01L22/34 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/00 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L2223/54406 ,  H01L2223/54453 ,  H01L2223/5446

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.

公开(公告)号：US09276010B2

公开(公告)日：2016-03-01

申请号：US14296496

申请日：2014-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Fang-Lan Chu

IPC: H01L29/88 ,  H01L21/336 ,  H01L27/115 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11573 ,  H01L21/28282 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7831 ,  H01L29/792

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a high-K metal gate (HKMG) integrated circuit that utilizes a replacement gate technology with low poly resistance and high program/erase speed. A silicide layer formed over top surfaces of the NVM device, after replacement gate process of the HKMG circuit prevents poly damage during contact formation and provides low gate resistance, thereby improving program/erase speed of the NVM device.

Abstract translation: 本公开涉及一种将非易失性存储器（NVM）嵌入高K金属栅（HKMG）集成电路中的结构和方法，其利用具有低多电阻和高编程/擦除速度的替代栅极技术。 在HKMG电路的更换栅极处理之后，在NVM器件的顶表面上形成的硅化物层防止接触形成期间的多晶硅损伤并且提供低栅极电阻，从而提高NVM器件的编程/擦除速度。

公开(公告)号：US20150333082A1

公开(公告)日：2015-11-19

申请号：US14296496

申请日：2014-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Fang-Lan Chu

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11573 ,  H01L21/28282 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7831 ,  H01L29/792

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a high-K metal gate (HKMG) integrated circuit that utilizes a replacement gate technology with low poly resistance and high program/erase speed. A silicide layer formed over top surfaces of the NVM device, after replacement gate process of the HKMG circuit prevents poly damage during contact formation and provides low gate resistance, thereby improving program/erase speed of the NVM device.

Abstract translation: 本公开涉及一种将非易失性存储器（NVM）嵌入高K金属栅（HKMG）集成电路中的结构和方法，其利用具有低多电阻和高编程/擦除速度的替代栅极技术。 在HKMG电路的更换栅极处理之后，在NVM器件的顶表面上形成的硅化物层防止接触形成期间的多晶硅损伤并且提供低栅极电阻，从而提高NVM器件的编程/擦除速度。

公开(公告)号：US09129823B2

公开(公告)日：2015-09-08

申请号：US13854507

申请日：2013-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots.

Abstract translation: 所描述的实施例提供了用于蚀刻半导体主体上的有源区域并且外延沉积覆盖有源区域的半导体层的方法和半导体器件区域。 这些方法可以减轻或消除随后与STI科技相关的制造过程中遇到的问题。

公开(公告)号：US12167594B2

公开(公告)日：2024-12-10

申请号：US16989778

申请日：2020-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chin Liu ,  Wei Cheng Wu ,  Yi Hsien Lu ,  Yu-Hsiung Wang ,  Juo-Li Yang

IPC: H01L21/82 ,  G11C16/04 ,  G11C16/12 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/788 ,  H10B10/00 ,  H10B41/42 ,  H10B41/49 ,  H10B41/50 ,  H10B99/00

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US11903191B2

公开(公告)日：2024-02-13

申请号：US17231204

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H10B41/30 ,  H01L21/28 ,  H01L27/105 ,  H01L21/8234 ,  H01L29/66 ,  H10B41/49 ,  H10B43/00 ,  H10B43/30 ,  H01L21/306 ,  H01L21/321 ,  H10B10/00

CPC classification number: H10B41/30 ,  H01L21/30604 ,  H01L21/3212 ,  H01L21/823462 ,  H01L27/105 ,  H01L29/40114 ,  H01L29/66545 ,  H10B41/49 ,  H10B43/00 ,  H10B43/30 ,  H10B10/18

Abstract: An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

公开(公告)号：US20230299010A1

公开(公告)日：2023-09-21

申请号：US17748640

申请日：2022-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Haklay Chuang ,  Yuan-Jen Lee ,  Nuo Xu ,  Fang-Lan Chu ,  Wei Cheng Wu

IPC: H01L23/544 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L24/80 ,  H01L24/08 ,  H01L2223/54426 ,  H01L2224/8013 ,  H01L2224/80948 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08147 ,  H01L2224/0213 ,  H01L25/0657

Abstract: In an embodiment, a method includes: receiving a first wafer and a second wafer, the first wafer including a first alignment mark, the first alignment mark including a first grid of first magnetic features, the second wafer including a second alignment mark, the second alignment mark including a second grid of second magnetic features; aligning the first alignment mark with the second alignment mark in an optical alignment process; after the optical alignment process, aligning the first alignment mark with the second alignment mark in a magnetic alignment process, north poles of the first magnetic features being aligned with south poles of the second magnetic features, south poles of the first magnetic features being aligned with north poles of the second magnetic features; and forming bonds between the first wafer and the second wafer.

公开(公告)号：US11631682B2

公开(公告)日：2023-04-18

申请号：US16860234

申请日：2020-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Hsin Chiu ,  Meng-Han Lin ,  Wei Cheng Wu

IPC: H01L27/11 ,  G06F30/398 ,  H01L23/528 ,  G11C29/50 ,  G11C29/08 ,  G11C29/04 ,  G11C29/12 ,  G06F30/39

Abstract: In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.

公开(公告)号：US11532694B2

公开(公告)日：2022-12-20

申请号：US17106409

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu ,  Te-An Chen

IPC: H01L49/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08 ,  H01L23/64 ,  H01L29/92 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/768

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a substrate having an isolation structure therein and a capacitor structure located on an upper top surface of the isolation structure. The capacitor structure comprises a first semiconductor structure and a second semiconductor structure respectively disposed on the upper surface of the isolation structure and separated by an insulator pattern.

公开(公告)号：US11424263B2

公开(公告)日：2022-08-23

申请号：US16695475

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/11575 ,  H01L29/06 ,  H01L21/76 ,  H01L27/11573 ,  H01L21/762 ,  H01L27/11565

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed within a substrate and a plurality of memory devices disposed within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. The first isolation structure has a protrusion extending outward from an upper surface of the first isolation structure. A logic wall is arranged on the protrusion and surrounds the plurality of memory devices.