公开(公告)号：US12154949B2

公开(公告)日：2024-11-26

申请号：US18317397

申请日：2023-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chien ,  Wen-Yen Chen ,  Li-Ting Wang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang

IPC: H01L29/10 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.

公开(公告)号：US20240387700A1

公开(公告)日：2024-11-21

申请号：US18786464

申请日：2024-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Liang-Yin Chen ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.

公开(公告)号：US20240387232A1

公开(公告)日：2024-11-21

申请号：US18785067

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh Chang ,  Jyh-Cherng Sheu ,  Chen-Fong Tsai ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/687 ,  H01L21/67 ,  H01L21/683

Abstract: A method includes mounting a first wafer on a first wafer chuck and mounting a second wafer on a second wafer chuck. The second wafer is brought into physical contact with the first wafer. A relative distance between the first wafer and the second wafer is monitored using a distance sensor. A pressure of a vacuum zone on the second wafer chuck is controlled using feedback from the distance sensor. The bonded first wafer and second wafer are removed from the first wafer chuck.

公开(公告)号：US12087592B2

公开(公告)日：2024-09-10

申请号：US18446416

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Fong Tsai ,  Ya-Lun Chen ,  Tsai-Yu Huang ,  Yahru Cheng ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/3105 ,  G03F7/16 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/31058 ,  G03F7/162 ,  G03F7/168 ,  H01L21/0276 ,  H01L21/31144

Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.

公开(公告)号：US20240274465A1

公开(公告)日：2024-08-15

申请号：US18643212

申请日：2024-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Kai Hsiao ,  Han-De Chen ,  Tsai-Yu Huang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/28008 ,  H01L21/76227 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/0649

Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region and forms a semiconductor fin.

公开(公告)号：US20240249944A1

公开(公告)日：2024-07-25

申请号：US18625651

申请日：2024-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sih-Jie Liu ,  Chun-Feng Nieh ,  Huicheng Chang

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7851 ,  H10B10/12

Abstract: A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the deep p-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET.

公开(公告)号：US11996412B2

公开(公告)日：2024-05-28

申请号：US17818598

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Li-Ting Wang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/94 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78 ,  H01L31/113

CPC classification number: H01L27/0924 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

公开(公告)号：US20240145596A1

公开(公告)日：2024-05-02

申请号：US18402173

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Kai-Hsuan Lee ,  I-Hsieh Wong ,  Cheng-Yu Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Syun-Ming Jang ,  Meng-Han Chou

IPC: H01L29/78 ,  H01L21/266 ,  H01L21/3115 ,  H01L21/764 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/266 ,  H01L21/31155 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28518

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

公开(公告)号：US20240136220A1

公开(公告)日：2024-04-25

申请号：US18401955

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

公开(公告)号：US20240120314A1

公开(公告)日：2024-04-11

申请号：US18390439

申请日：2023-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huicheng Chang ,  Jyh-Cherng Sheu ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/265 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L24/83 ,  H01L21/265 ,  H01L21/6835 ,  H01L21/7806 ,  H01L25/50

Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.