中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

796 records (took 0.031 seconds)

    Predictive, adaptive power supply for an integrated circuit under test
    112.
    发明申请
    Predictive, adaptive power supply for an integrated circuit under test 有权

    公开(公告)号：US20060022699A1

    公开(公告)日：2006-02-02

    申请号：US11237092

    申请日：2005-09-27

    Applicant: Benjamin Eldridge ,  Charles Miller

    Inventor： Benjamin Eldridge ,  Charles Miller

    IPC: G01R31/26

    CPC classification number: G06F1/26 ,  G01R31/2851 ,  G01R31/31721 ,  G01R31/31905 ,  G01R31/31924

    Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.

    Method for forming microelectronic spring structures on a substrate
    113.
    发明申请
    Method for forming microelectronic spring structures on a substrate 审中-公开
    在基板上形成微电子弹簧结构的方法

    公开(公告)号：US20060019027A1

    公开(公告)日：2006-01-26

    申请号：US11189954

    申请日：2005-07-25

    Applicant: Benjamin Eldridge ,  Stuart Wenzel

    Inventor： Benjamin Eldridge ,  Stuart Wenzel

    IPC: H05K3/00 ,  C23C28/00

    CPC classification number: G01R1/06716 ,  G01R1/0483 ,  G01R1/06727 ,  G01R1/06733 ,  G01R1/07342 ,  G01R3/00 ,  H01L23/4822 ,  H01L24/72 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01R12/52 ,  H01R13/24 ,  H01R13/2407 ,  H05K3/4092 ,  H05K7/1069 ,  Y10T29/49147 ,  H01L2924/00

    Abstract: A method for fabricating microelectronic spring structures is disclosed. In an initial step of the method, a layer of sacrificial material is formed over a substrate. Then, a contoured surface is developed in the sacrificial material, such as by molding the sacrificial material using a mold or stamp. The contoured surface provides a mold for at least one spring form, and preferably for an array of spring forms. If necessary, the sacrificial layer is then cured or hardened. A layer of spring material is deposited over the contoured surface of the sacrificial material, in a pattern to define at least one spring form, and preferably an array of spring forms. The sacrificial material is then at least partially removed from beneath the spring form to reveal at least one freestanding spring structure. A separate conducting tip is optionally attached to each resulting spring structure, and each structure is optionally plated or covered with an additional layer or layers of material, as desired. An alternative method for making a resilient contact structure using the properties of a fluid meniscus is additionally disclosed. In an initial step of the alternative method, a layer of material is provided over a substrate. Then, a recess is developed in the material, and fluid is provided in the recess to form a meniscus. The fluid is cured or hardened to stabilize the contoured shape of the meniscus. The stabilized meniscus is then used to define a spring form in the same manner as the molded surface in the sacrificial material.

    Abstract translation: 公开了一种用于制造微电子弹簧结构的方法。 在该方法的初始步骤中，在衬底上形成牺牲材料层。 然后，在牺牲材料中形成轮廓表面，例如通过使用模具或印模模制牺牲材料。 轮廓表面提供用于至少一种弹簧形式的模具，并且优选地用于弹簧形式的阵列。 如果需要，则牺牲层被固化或硬化。 弹性材料层以牺牲材料的轮廓表面沉积在图案中以限定至少一种弹簧形式，并且优选地是弹簧形式的阵列。 然后，牺牲材料至少部分地从弹簧形式的下方移除，以露出至少一个独立的弹簧结构。 单独的导电尖端任选地附接到每个所得到的弹簧结构，并且根据需要，每个结构可选地被电镀或覆盖有附加的一层或多层材料。 还公开了使用流体弯液面的性质制造弹性接触结构的替代方法。 在替代方法的初始步骤中，在衬底上提供一层材料。 然后，在该材料中形成凹部，并且在凹部中设置流体以形成弯液面。 流体被固化或硬化以稳定弯液面的轮廓形状。 然后将稳定的弯液面用于与牺牲材料中的模制表面相同的方式限定弹簧形式。

    Special contact points for accessing internal circuitry of an intergrated circuit
    114.
    发明申请
    Special contact points for accessing internal circuitry of an intergrated circuit 审中-公开
    用于访问集成电路内部电路的特殊接点

    公开(公告)号：US20060006384A1

    公开(公告)日：2006-01-12

    申请号：US11221231

    申请日：2005-09-06

    Applicant: Benjamin Eldridge ,  Igor Khandros ,  David Pedersen ,  Ralph Whitten

    Inventor： Benjamin Eldridge ,  Igor Khandros ,  David Pedersen ,  Ralph Whitten

    IPC: H01L23/58

    CPC classification number: G01R1/07307 ,  G01R31/2884 ,  G01R31/31723 ,  H01L22/32 ,  H01L23/50 ,  H01L23/60 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2224/29099 ,  H01L2924/00

    Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g., nonvolatile circuits) at the die or package level. The special contact points may also be used to select redundant circuits for faulty circuits.

    Abstract translation: 本发明的一个实施例涉及包括接合焊盘和特殊接触焊盘或点的集成电路。 接合焊盘用于将集成电路作为整体与外部电路接口，并且将被连接到封装或电路板。 接合焊盘以预定的对准方式设置在管芯上，例如外围，栅格或中心对准。 特殊接触焊盘用于向内部电路提供外部测试模式和/或外部监测测试内部电路的结果。 特别的接触垫可以有利地以高度的位置自由度位于集成电路上。 对于一个实施例，特殊接触焊盘可以在与焊盘不同于对准的位置处设置在管芯上。 特殊的接触焊盘可以小于接合焊盘，以便不会由于特殊的接触垫而增加管芯的尺寸。 特殊接触点也可以用于在芯片或封装级别外部编程内部电路（例如非易失性电路）。 特殊接触点也可用于选择故障电路的冗余电路。

    Intelligent probe card architecture
    116.
    发明申请
    Intelligent probe card architecture 有权
    智能探针卡架构

    公开(公告)号：US20050237073A1

    公开(公告)日：2005-10-27

    申请号：US10828755

    申请日：2004-04-21

    Applicant: Charles Miller ,  Matthew Chraft ,  Roy Henson

    Inventor： Charles Miller ,  Matthew Chraft ,  Roy Henson

    IPC: G01R1/073 ,  G01R1/36 ,  G01R31/02 ,  G01R31/28 ,  G01R31/319 ,  G01R35/00

    CPC classification number: G01R31/31905 ,  G01R1/07385 ,  G01R1/36 ,  G01R31/2889 ,  G01R35/00

    Abstract: A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.

    Abstract translation: 用于晶片测试系统的探针卡具有多个板上特征，使扇出测试系统控制器通道以测试晶片上的多个DUT，同时限制扇出对测试结果的不期望的影响。 探头卡的板载功能包括以下一个或多个功能：（a）通过将电阻器与每个DUT输入串联放置来隔离故障DUT提供的DUT信号隔离; （b）与每个DUT电源引脚串联的开关，限流器或稳压器提供的DUT电源隔离，以将电源与失效的DUT隔离; （c）使用板载微控制器或FPGA提供的自检; （d）作为探针卡的一部分提供的堆叠子卡，以适应额外的板上测试电路; 和（e）在基板PCB和探针卡的子卡之间使用接口总线或测试系统控制器以最小化基板PCB和子卡之间或基板和测试系统控制器之间的接口线的数量 。

    Predictive, adaptive power supply for an integrated circuit under test
    117.
    发明授权
    Predictive, adaptive power supply for an integrated circuit under test 失效
    用于被测集成电路的预测，自适应电源

    公开(公告)号：US06949942B2

    公开(公告)日：2005-09-27

    申请号：US10725824

    申请日：2003-12-01

    Applicant: Benjamin N. Eldridge ,  Charles A. Miller

    Inventor： Benjamin N. Eldridge ,  Charles A. Miller

    IPC: G01R31/26 ,  G01R31/28 ,  G01R31/317 ,  G01R31/319 ,  G06F1/26 ,  H01L21/66 ,  G01R31/02

    CPC classification number: G06F1/26 ,  G01R31/2851 ,  G01R31/31721 ,  G01R31/31905 ,  G01R31/31924

    Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.

    Abstract translation: 主电源将电流通过路径阻抗提供给被测集成电路器件（DUT）的电源端子。 在测试期间，DUT对电源输入端的电流需求暂时增加了在测试期间施加到DUT的时钟信号的随后边缘，作为IC开关中的晶体管响应于时钟信号的边缘。 为了限制电源输入端子的电压变化（噪声），辅助电源为电源输入端子提供额外的电流脉冲，以满足在时钟信号的每个周期期间增加的需求。 电流脉冲的大小是在该时钟周期期间电流需求的预测增加以及由反馈电路控制的适配信号的大小的函数，以限制在DUT的功率输入端产生的电压变化。

Patent Agency Ranking