公开(公告)号：US20050156165A1

公开(公告)日：2005-07-21

申请号：US11000586

申请日：2004-11-30

申请人： Benjamin Eldridge ,  Igor Khandros ,  David Pedersen ,  Ralph Whitten

发明人： Benjamin Eldridge ,  Igor Khandros ,  David Pedersen ,  Ralph Whitten

IPC分类号： G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498 ,  H01L23/544 ,  H05K3/20 ,  H05K3/34 ,  H01L23/58 ,  G01R31/02 ,  H01L29/10

CPC分类号： G01R1/07307 ,  G01R1/07342 ,  G01R1/07371 ,  G01R31/2884 ,  G01R31/2886 ,  H01L22/32 ,  H01L22/34 ,  H01L23/49811 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/13 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/20 ,  H05K3/3421 ,  H01L2924/00014 ,  H01L2924/00

摘要： One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die. The test die can be used to test multiple product die on one or more wafers.

摘要翻译： 本发明的一个实施例涉及一种用于测试产品模具的产品电路的测试组件。 在一个实施例中，测试组件包括在测试模具和用于将测试模具电耦合到与测试模具通信的主机控制器的互连衬底。 测试模具可以根据设计方法设计，包括在统一设计中同时设计测试电路和产品电路的步骤。 测试电路可以设计成为相应的产品电路提供高度的故障覆盖，通常不考虑测试电路所需的硅面积的量。 然后，设计方法将统一设计分为测试模具和产品模具。 测试芯片包括测试电路，产品芯片包括产品电路。 然后可以在单独的半导体晶片上制造产品和测试裸片。 通过将产品电路和测试电路划分为单独的管芯，可以在产品管芯上消除或最小化嵌入式测试电路。 这将倾向于减小产品模具的尺寸并降低制造产品模具的成本，同时保持产品模具内的产品电路的高度测试覆盖。 测试模具可用于在一个或多个晶片上测试多个产品模具。

公开(公告)号：US06752198B2

公开(公告)日：2004-06-22

申请号：US10308675

申请日：2002-12-03

申请人： Teunis Heijkoop ,  Ian Robert Dick ,  Bernard Bednarz ,  Geoffrey Martin Goss ,  Philip David Pedersen ,  Robert Sidney Brunton ,  William Trickett Wright

发明人： Teunis Heijkoop ,  Ian Robert Dick ,  Bernard Bednarz ,  Geoffrey Martin Goss ,  Philip David Pedersen ,  Robert Sidney Brunton ,  William Trickett Wright

IPC分类号： B22D1904

CPC分类号： B22C9/06 ,  B22C9/00 ,  B22C9/22 ,  B22D19/08 ,  B22D19/10 ,  B22D19/16

摘要： Bimetallic plate is produced by providing a substrate of a first metal and, with the preheated substrate positioned in a mold cavity with a major surface of the substrate facing upwardly and to fill a portion of the depth of the cavity, a second metal is cast against that surface to form a cladding component and, with the substrate, to form the bimetallic plate. Prior to the cladding being cast, the major surface is rendered substantially oxide-free and is protected against oxidation. The cladding is cast by a melt, of a composition required for it, being poured at a superheated temperature whereby, with the preheating of the substrate, an overall heat energy balance is achieved between the substrate and the cladding. The heat energy balance causes a diffusion bond to be achieved between the major surface of the substrate and the cladding, and attainment of the energy balance is facilitated by causing the melt to enter the mold cavity through a series of gates which provide communication between at least one runner and the mold cavity. The series of gates is disposed laterally with respect to flow of the melt therethrough whereby the melt forms a laterally extending melt front. Attainment of the heat energy balance is further facilitated by causing the melt front to advance away from the gates, over the substrate surface, at a rate which is substantially uniform across the lateral extent of the front.

摘要翻译： 双金属板通过提供第一金属的基底而产生，并且预热的基底定位在模腔中，基底的主表面朝上并填充腔的一部分深度，第二金属被铸造成抵抗 该表面形成包层部件，并与基板一起形成双金属板。 在包层被铸造之前，主表面基本上不含氧化物，并被保护免受氧化。 包层由其所需组合物的熔体铸造，在过热温度下浇注，由此通过衬底的预热，在衬底和包层之间实现总的热能平衡。 热能平衡导致在衬底的主表面和包层之间实现扩散接合，并且通过使熔体通过一系列栅极进入模腔来实现能量平衡，这些栅极至少提供了至少 一个跑步者和模具腔。 一系列门相对于熔体的流动横向设置在其中，由此熔体形成横向延伸的熔体前沿。 通过使熔体前沿在基板表面上以跨过前部的横向范围基本均匀的速率前进离开门，进一步促进了热能平衡的获得。

公开(公告)号：US20110054654A1

公开(公告)日：2011-03-03

申请号：US12552829

申请日：2009-09-02

申请人： Andrew Nicholas John Brojer Phillips ,  Michael David Pedersen

发明人： Andrew Nicholas John Brojer Phillips ,  Michael David Pedersen

IPC分类号： G06F17/50 ,  G06G7/58 ,  G06G7/62

摘要： Creating genetic devices for use in micro-organisms or other biological systems is described. In an embodiment a computer system receives at a program editor, input specifying a plurality of part designs, at least some of which comprise part properties expressed as logical variables; and the input also specifies constraints on the logical variables. For example, the input is a computer program which specifies constraints on the logical variables which, for example, relate to properties of the DNA sequences such as reactions and biological behaviors. In an example, a compiler resolves the constraints using a database of genetic parts in order to generate candidate parts for the proposed genetic device. In examples the sequences of genetic parts are translated into reactions and simulated using an automated simulator and/or implemented in a living cell or other biological system. In embodiments the compiler also uses a database of reactions.

摘要翻译： 描述了创建用于微生物或其他生物系统的遗传装置。 在一个实施例中，计算机系统在节目编辑器处接收指定多个部分设计的输入，其中至少一些包括表示为逻辑变量的部分属性; 并且输入也指定对逻辑变量的约束。 例如，输入是指定逻辑变量的约束的计算机程序，其例如涉及DNA序列的性质，例如反应和生物行为。 在一个示例中，编译器使用遗传部分的数据库解决约束，以便生成所提出的遗传设备的候选部分。 在实例中，遗传部分的序列被翻译成反应并使用自动模拟器模拟和/或在活细胞或其他生物系统中实现。 在实施例中，编译器还使用反应数据库。

公开(公告)号：US20070269909A1

公开(公告)日：2007-11-22

申请号：US11749084

申请日：2007-05-15

申请人： Douglas Ondricek ,  David Pedersen

发明人： Douglas Ondricek ,  David Pedersen

IPC分类号： H01L21/677

CPC分类号： G01R1/0433 ,  G01R1/0408 ,  G01R1/0466 ,  G01R31/01 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2893 ,  H01L21/67294 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/5385 ,  H01L23/544 ,  H01L24/72 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/73251 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/16152 ,  H05K3/325 ,  H05K2201/09472 ,  H01L2924/00 ,  H01L2224/72

摘要： Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The identification code may be applied to the carrier before or after depositing the singulated die into the carrier. The carrier may be used in testing the singulated die and may include a plurality of singulated die or just one singulated die. In another example of a method of the invention, an identification code is applied to a die. The die is deposited into a carrier which holds the die. The die comprises an integrated circuit, and the carrier holds the die in singulated form. Typically the die is placed in the carrier without any packaging which may protect the die. The identification code may be applied to the die before or after it is deposited into the carrier.

摘要翻译： 用于处理包括集成电路的至少一个管芯的方法。 在本发明的方法的一个示例中，将识别码应用于载体。 单片模具沉积在保持单模模具的载体中。 单片模具包括集成电路。 可以在将分割的裸片沉积到载体中之前或之后将识别码应用于载体。 载体可以用于测试单个模具，并且可以包括多个单个模具或仅一个单模模具。 在本发明方法的另一个例子中，将识别码应用于管芯。 模具沉积在保持模具的载体中。 芯片包括集成电路，并且载体以单模形式保持模具。 通常，模具被放置在载体中而没有任何可保护模具的包装。 识别码可以在将其沉积到载体中之前或之后施加于该芯片。

公开(公告)号：US08272250B2

公开(公告)日：2012-09-25

申请号：US12385691

申请日：2009-04-16

申请人： Shiliang Wang ,  David Pedersen

发明人： Shiliang Wang ,  David Pedersen

IPC分类号： G01N27/04

CPC分类号： G01N27/127

摘要： An effective sensor for indicating exposure to a toxic gas includes a non-conductive, inert substrate such as glass or polyethylene, a two-dimensional film of nanoparticles of a conductive metal such as silver or copper on the substrate and an electrode connected to each end of the film. When an electrical current passes through the film and the sensor is exposed to a toxic gas, changes in the electrical resistance of the film provides an indication of the presence of the toxic gas.

摘要翻译： 用于指示暴露于有毒气体的有效传感器包括非导电惰性基底，例如玻璃或聚乙烯，基底上的诸如银或铜的导电金属的纳米颗粒的二维膜和连接到每一端的电极 的电影。 当电流通过膜并且传感器暴露于有毒气体时，膜的电阻变化提供有毒气体的存在的指示。

公开(公告)号：US20070285114A1

公开(公告)日：2007-12-13

申请号：US11733562

申请日：2007-04-10

申请人： David Pedersen ,  Benjamin Eldridge ,  Igor Khandros

发明人： David Pedersen ,  Benjamin Eldridge ,  Igor Khandros

IPC分类号： G01R31/02

CPC分类号： H01L25/16 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/0408 ,  G01R1/0433 ,  G01R1/06711 ,  G01R1/07342 ,  G01R1/07378 ,  G01R31/01 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L22/20 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/19043 ,  H05K1/141 ,  H05K3/20 ,  H05K3/325 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/368 ,  H05K3/4015 ,  H05K2201/09472 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/48

摘要： Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

摘要翻译： 提供产品和组件用于可插拔地接收从电子部件（例如半导体器件）延伸的细长互连元件，例如弹簧接触元件。 插座基板设置有用于接收从电子部件延伸的细长互连元件的端部的捕获垫。 公开了各种捕获垫结构。 通过邻近插座基板表面的导电迹线提供与外部设备的连接。 插座基板可以由支撑基板支撑。 在特别优选的实施例中，捕获垫直接形成在诸如印刷电路板的主要基底上。

公开(公告)号：US20070013401A1

公开(公告)日：2007-01-18

申请号：US11458375

申请日：2006-07-18

申请人： Igor Khandros ,  David Pedersen

发明人： Igor Khandros ,  David Pedersen

IPC分类号： G01R31/26

CPC分类号： G01R31/2886 ,  G01R31/287 ,  G01R31/2874 ,  G01R31/318511 ,  H01L2924/01078 ,  H01L2924/01079

摘要： Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. Physical alignment techniques are also described.

摘要翻译： 用于执行半导体器件的晶片级老化和测试的技术包括具有有源电子部件的测试基板，例如安装到互连基板或并入其中的ASIC，实现ASIC和多个器件之间的互连的金属弹簧接触元件 在测试晶片（WUT）上的测试（DUT）都被置于真空容器中，使得ASIC可以在与DUT的老化温度无关并且显着低于DUT的老化温度的温度下工作。 弹簧接触元件可以被安装到DUT或ASIC上，并且可以扇出来放松对ASIC和DUT的对准和互连的容限约束。 还描述了物理对准技术。

公开(公告)号：US20060006384A1

公开(公告)日：2006-01-12

申请号：US11221231

申请日：2005-09-06

申请人： Benjamin Eldridge ,  Igor Khandros ,  David Pedersen ,  Ralph Whitten

发明人： Benjamin Eldridge ,  Igor Khandros ,  David Pedersen ,  Ralph Whitten

IPC分类号： H01L23/58

CPC分类号： G01R1/07307 ,  G01R31/2884 ,  G01R31/31723 ,  H01L22/32 ,  H01L23/50 ,  H01L23/60 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2224/29099 ,  H01L2924/00

摘要： One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g., nonvolatile circuits) at the die or package level. The special contact points may also be used to select redundant circuits for faulty circuits.

摘要翻译： 本发明的一个实施例涉及包括接合焊盘和特殊接触焊盘或点的集成电路。 接合焊盘用于将集成电路作为整体与外部电路接口，并且将被连接到封装或电路板。 接合焊盘以预定的对准方式设置在管芯上，例如外围，栅格或中心对准。 特殊接触焊盘用于向内部电路提供外部测试模式和/或外部监测测试内部电路的结果。 特别的接触垫可以有利地以高度的位置自由度位于集成电路上。 对于一个实施例，特殊接触焊盘可以在与焊盘不同于对准的位置处设置在管芯上。 特殊的接触焊盘可以小于接合焊盘，以便不会由于特殊的接触垫而增加管芯的尺寸。 特殊接触点也可以用于在芯片或封装级别外部编程内部电路（例如非易失性电路）。 特殊接触点也可用于选择故障电路的冗余电路。

公开(公告)号：US06766348B1

公开(公告)日：2004-07-20

申请号：US09365631

申请日：1999-08-03

申请人： Charles Combs ,  Jeffrey Gold ,  Brian Mair ,  David Pedersen ,  David Schear

发明人： Charles Combs ,  Jeffrey Gold ,  Brian Mair ,  David Pedersen ,  David Schear

IPC分类号： G06F1700

CPC分类号： G06F9/5083

摘要： A method and system for allocating distributed resources connected to a computer network to application programs running on computers attached to the communications network. The distributed resource allocator system comprises a number of identical processes running on one or more computers attached to the communications network. Application programs request allocation of resources from a local distributed resource allocator system process running using a resource allocator applications programming interface. Application programs request allocation of resource from a remote distributed resource allocator system process via a resource allocator access protocol. The distributed resource allocator system is fault-tolerant and provides contention control and load balancing. The resource allocator system also manages information about the capacities and capabilities of resources connected to the communications network. Application programs can thus be easily written to make use of distributed resources connected to a communications network without having to manage global network information and without needing complex contention control and load balancing subroutines.

摘要翻译： 用于将连接到计算机网络的分布式资源分配给在连接到通信网络的计算机上运行的应用程序的方法和系统。 分布式资源分配器系统包括在连接到通信网络的一个或多个计算机上运行的多个相同进程。 应用程序从使用资源分配器应用程序编程接口运行的本地分布式资源分配器系统进程请求分配资源。 应用程序通过资源分配器访问协议请求从远程分布式资源分配器系统进程分配资源。 分布式资源分配器系统是容错的，提供争用控制和负载平衡。 资源分配器系统还管理有关连接到通信网络的资源的容量和能力的信息。 因此，应用程序可以容易地被写入以利用连接到通信网络的分布式资源，而不必管理全局网络信息，并且不需要复杂的争用控制和负载均衡子例程。

公开(公告)号：US20060244469A1

公开(公告)日：2006-11-02

申请号：US11426621

申请日：2006-06-27

申请人： Mohammad Eslamy ,  David Pedersen ,  Harry Cobb

发明人： Mohammad Eslamy ,  David Pedersen ,  Harry Cobb

IPC分类号： G01R31/02

CPC分类号： G01R31/2886 ,  G01R3/00 ,  Y10T29/49004 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49171 ,  Y10T29/49178 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211

摘要： A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.

摘要翻译： 一种制造大面积多元件接触器的方法。 提供分段接触器用于测试晶片上的半导体器件，其包括安装到衬底的多个接触器单元。 接触器单元被形成，测试和组装到背衬基板上。 接触器单元可以包括横向延伸的引线以连接到诸如老化板的外部仪器。 接触器单元包括诸如焊盘的导电区域，其被放置成与被测器件上的导电端子接触。