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    METHOD FOR PREPARING POWER DIODE
    122.
    发明申请
    METHOD FOR PREPARING POWER DIODE 有权
    制备功率二极管的方法

    公开(公告)号：US20160307994A1

    公开(公告)日：2016-10-20

    申请号：US14902270

    申请日：2014-10-22

    Applicant: CSMC Technologies Fab2 Co., Ltd.

    Inventor： Genyi Wang ,  Xiaoshe Deng ,  Shengrong Zong ,  Dongfei Zhou

    IPC: H01L29/06 ,  H01L21/266 ,  H01L29/10 ,  H01L21/311 ,  H01L21/324 ,  H01L21/027 ,  H01L29/66 ,  H01L21/265

    CPC classification number: H01L29/0619 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31116 ,  H01L21/32105 ,  H01L21/32137 ,  H01L21/324 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/6606 ,  H01L29/66136 ,  H01L29/66204 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7811 ,  H01L29/8611

    Abstract: A method for preparing a power diode, including: providing a substrate (10), growing a N type layer (20) on the front surface of the substrate (10); forming a terminal protecting ring; forming an oxide layer (30), knot-pushing to the terminal protecting ring; forming a gate oxide layer (60), depositing a poly-silicon layer (70) on the gate oxide layer (60); depositing a SiO2 layer (80) on the surface of the poly-silicon layer (70) and a oxide layer (50); forming a N type heavy doped region (92); forming a P+ region; removing a photoresist, implanting P type ions using the SiO2 layer (80) as a mask layer, and forming a P type body region; heat annealing; forming a side wall structure in the opening of the poly-silicon layer (70), the gate oxide layer (60) being etched, and removing the SiO2 layer (80); and processing a front surface metallization and a back surface metallization treatment. According to the method for preparing the power diode, by adjusting the isotropy etching level of the SiO2 layer and the ion implanting dose and energy, the threshold voltage of a DMOS structure can be adjusted, and the adjustment of the forward voltage drop for the device can be achieved.

    Abstract translation: 一种制备功率二极管的方法，包括：提供衬底（10），在衬底（10）的前表面上生长N型层（20）; 形成端保护环; 形成氧化物层（30），向所述端子保护环打结; 形成栅极氧化物层（60），在所述栅极氧化物层（60）上沉积多晶硅层（70）。 在所述多晶硅层（70）的表面和氧化物层（50）上沉积SiO 2层（80）; 形成N型重掺杂区域（92）; 形成P +区; 去除光致抗蚀剂，使用SiO 2层（80）作为掩模层注入P型离子，形成P型体区; 热退火; 在所述多晶硅层（70）的开口部形成侧壁结构，蚀刻所述栅极氧化物层（60），除去所述SiO 2层（80）。 以及处理前表面金属化和背面金属化处理。 根据制备功率二极管的方法，通过调整SiO2层的各向同性蚀刻水平和离子注入剂量和能量，可以调整DMOS结构的阈值电压，并调整器件的正向压降 可以实现。

    TEST METHOD AND SYSTEM FOR CUT-IN VOLTAGE
    123.
    发明申请
    TEST METHOD AND SYSTEM FOR CUT-IN VOLTAGE 有权
    用于切入电压的测试方法和系统

    公开(公告)号：US20150338455A1

    公开(公告)日：2015-11-26

    申请号：US14759370

    申请日：2013-12-31

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Ming WANG ,  Xiaoqian LIAN ,  Yaojun LIN ,  Wenhui XU ,  Hanshun CHEN

    IPC: G01R31/26

    CPC classification number: G01R31/2621 ,  G01R31/2623

    Abstract: A test method and system for cut-in voltage. The method comprises: coarse scanning of the cut-in voltage: a grid voltage, i.e., the cut-in voltage, is quickly determined when a drain terminal current is greater than a target current for the first time (100); accurate scanning of the cut-in voltage: a scanning step length is shortened continuously until the scanning step length is shorter than a preset step length, and each time the scanning step length is shortened, the scanning is conducted according to the current shortened scanning step length on the basis of the cut-in voltage determined in the former time, and then the cut-in voltage under the condition of the current shortened scanning step length is determined again (200). The scanning voltage is automatically increased or decreased by the test method and system through adding high resolution and high precision test conversion into a second scanning test, and therefore the testing of the cut-in voltage becomes more efficient and more accurate.

    Abstract translation: 一种插入电压的测试方法和系统。 该方法包括：当第一次（100）漏极端电流大于目标电流时，快速确定切入电压的粗扫描：电网电压即插入电压; 切入电压的准确扫描：扫描步长连续缩短直到扫描步长短于预设步长，并且每当扫描步长缩短时，根据当前缩短的扫描步骤进行扫描 根据先前确定的切入电压的长度，然后再次确定在当前缩短扫描步长的条件下的切入电压（200）。 通过将高分辨率和高精度的测试转换添加到第二扫描测试中，通过测试方法和系统自动地增加或减少扫描电压，因此切入电压的测试变得更有效和更准确。

    Fabrication method for semiconductor device and semiconductor device
    124.
    发明授权
    Fabrication method for semiconductor device and semiconductor device 有权
    半导体器件和半导体器件的制造方法

    公开(公告)号：US09040410B2

    公开(公告)日：2015-05-26

    申请号：US14130482

    申请日：2013-05-10

    Applicant: CSMC Technologies Fab2 Co., Ltd.

    Inventor： Xin Yang

    IPC: H01L23/544 ,  G03F7/20 ,  G03F9/00 ,  H01L21/00

    CPC classification number: H01L23/544 ,  G03F7/20 ,  G03F9/708 ,  H01L21/00 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A fabrication method for semiconductor devices is provided. The method comprises: depositing a dielectric layer that includes a plurality of functional layers, and forming a contact hole, or through hole, and a metal layer. The forming of the contact hole, or through hole, and the metal layer comprises performing photolithography on regions corresponding to a marking label for the photolithography of the dielectric layer and the metal layer. On at least one of the functional layers, the performing photolithography on regions corresponding to a marking label for the photolithography comprises limiting the photolithography to the metal layer thereof. A semiconductor device thus fabricated is also provided. The method and device do not affect the reading of the marking label, and also can avoid the problem of defocusing in the vicinity of the marking label.

    Abstract translation: 提供了半导体器件的制造方法。 该方法包括：沉积包括多个功能层的介电层，以及形成接触孔或通孔以及金属层。 接触孔或通孔以及金属层的形成包括在对应于用于电介质层和金属层的光刻的标记标签的区域上进行光刻。 在至少一个功能层上，对应于用于光刻的标记标签的区域上的执行光刻包括将光刻限制到其金属层。 还提供了如此制造的半导体器件。 该方法和装置不影响标记标签的读数，也可以避免标记标签附近散焦的问题。

    Laterally diffused metal oxide semiconductor device and method for preparing the same
    125.
    发明授权
    Laterally diffused metal oxide semiconductor device and method for preparing the same 有权

    公开(公告)号：US12272749B2

    公开(公告)日：2025-04-08

    申请号：US17789628

    申请日：2020-09-04

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Jingchuan Zhao ,  Zhili Zhang ,  Sen Zhang

    IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

    Abstract: Disclosed are a laterally diffused metal oxide semiconductor device and a method for preparing the same. The device includes a substrate (101) of a first conductivity type, a drift region (102) of a second conductivity type, a longitudinal floating field plate array and a plurality of implantation regions (103) of the first conductivity type. The drift region is located in the substrate of the first conductivity type. The longitudinal floating field plate array includes a plurality of longitudinal floating field plate structures (104) arranged at intervals in rows and columns. Each longitudinal floating field plate structures includes a dielectric layer (1041) disposed on an inner surface of a trench and a conductive layer (1042) filling the trench. The plurality of implantation regions are located in the drift region of, each implantation region is located between two adjacent longitudinal floating field plate structures in each row.

    LDMOS device and method for preparation thereof
    128.
    发明授权
    LDMOS device and method for preparation thereof 有权

    公开(公告)号：US12205996B2

    公开(公告)日：2025-01-21

    申请号：US17766406

    申请日：2020-08-18

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Huajun Jin ,  Guipeng Sun

    IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

    Abstract: The present invention relates to an LDMOS device and a method of forming the device, in which a barrier layer includes n etch stop layers. Insulating layers are formed between adjacent etch stop layers. Since an interlayer dielectric layer and the insulating layers are both oxides that differ from the material of the etch stop layers, etching processes can be stopped at the n etch stop layers when they are proceeding in the oxides, thus forming n field plate holes terminating at the respective n etch stop layers. A lower end of the first field plate hole proximal to a gate structure is closest to a drift region, and a lower end of the n-th field plate hole proximal to a drain region is farthest from the drift region. With this arrangement, more uniform electric field strength can be obtained around front and rear ends of the drift region, resulting in an effectively improved electric field distribution throughout the drift region and thus in an increased breakdown voltage.

    SEMICONDUCTOR DEVICE HAVING SPLIT GATE STRUCTURE AND MANUFACTURING METHOD THEREFOR
    130.
    发明公开
    SEMICONDUCTOR DEVICE HAVING SPLIT GATE STRUCTURE AND MANUFACTURING METHOD THEREFOR 审中-公开

    公开(公告)号：US20240304717A1

    公开(公告)日：2024-09-12

    申请号：US18284052

    申请日：2021-08-10

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： DONG FANG ,  KUI XIAO

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7813 ,  H01L29/66484 ,  H01L29/66734 ,  H01L29/7831

    Abstract: A semiconductor device having a split gate structure and a method for manufacturing the same. The method includes: obtaining a base formed with a trench; forming a trench wall oxide isolation dielectric on the inner surface of the trench, and forming a split gate by filling the trench with a split gate material; forming a first oxide isolation dielectric on the split gate; forming a silicon nitride isolation dielectric on the first oxide isolation dielectric; filling a second oxide isolation dielectric above the split gate in the trench in the position where the silicon nitride isolation dielectric is not formed; and forming a control gate on the second oxidation isolation dielectric. The isolation structure between the split gate and the control gate is a multi-dielectric structure which has a higher gate-source voltage resistance compared to the those using a single layer of oxide dielectric.

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