公开(公告)号：US09235068B2

公开(公告)日：2016-01-12

申请号：US14271641

申请日：2014-05-07

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert Manouvrier

IPC: G02F1/025 ,  G02F1/225 ,  G02F1/21 ,  G02B6/12 ,  G02F1/01

CPC classification number: G02F1/025 ,  G02B2006/12142 ,  G02F1/0123 ,  G02F1/2257 ,  G02F2001/212

Abstract: A semiconductor electro-optical phase shifter may include a first optical action zone having a minimum doping level, a first lateral zone and a central zone flanking the first optical action zone along a first axis, doped respectively at first and second conductivity types so as to form a P-I-N junction between the first lateral zone and the central zone. The phase shifter may include a second optical action zone having a threshold doping level, and a second lateral zone flanking the second optical action zone with the central zone along the first axis doped at the first conductivity type so as to form a P-I-N junction between the second lateral zone and the central zone.

Abstract translation: 半导体电光移相器可以包括分别以第一和第二导电类型掺杂的具有最小掺杂水平的第一光学作用区域，第一横向区域和沿着第一轴线的第一光学作用区域的侧面的中心区域，以便 在第一侧向区域和中心区域之间形成PIN结。 移相器可以包括具有阈值掺杂水平的第二光学作用区域和位于第二光学作用区域的第二侧向区域，其中中心区域沿着以第一导电类型掺杂的第一轴线形成PIN结， 第二横向区域和中心区域。

公开(公告)号：US09230950B2

公开(公告)日：2016-01-05

申请号：US13859418

申请日：2013-04-09

Applicant: STMICROELECTRONICS SA

Inventor： Philippe Galy ,  Jean Jimenez

IPC: H01L27/02 ,  H01L21/77 ,  H01L27/12 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/43

CPC classification number: H01L27/0207 ,  H01L21/76264 ,  H01L21/77 ,  H01L27/088 ,  H01L27/1211 ,  H01L29/0692 ,  H01L29/435 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7825

Abstract: At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks.

Abstract translation: 至少三个导电块设置在隔离区内; 并且它们中的至少两个被隔离区域的一部分相互分离和电容耦合。 它们中的至少两个是半导体，具有相反的导电性或相同类型的导电性，但是具有不同浓度的掺杂剂，并且这些掺杂物的两侧之间相互接触。 这些块在隔离区域内的相互排列，它们的导电类型及其掺杂剂的浓度形成至少一个电子模块。 一些块定义输入和输出块。

公开(公告)号：US09219095B2

公开(公告)日：2015-12-22

申请号：US14489698

申请日：2014-09-18

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Sebastien Jouan ,  Laurent Frey

IPC: H01L27/146 ,  H01L29/49 ,  H01L31/107

CPC classification number: H01L27/14645 ,  H01L27/14614 ,  H01L27/14621 ,  H01L27/14636 ,  H01L27/14649 ,  H01L27/14685 ,  H01L27/14689 ,  H01L29/4916 ,  H01L31/107

Abstract: An integrated circuit includes a substrate and an interconnect part above the substrate, and further includes a photosensitive region in the substrate. A filter is provided aligned with the photosensitive region. The filter is formed by at least one layer of filter material. In one implementation for front side illumination, the layer of filter material is positioned above the photosensitive region between the interconnect part and the substrate. In another implementation for back side illumination, the layer of filter material is positioned below the photosensitive region opposite the interconnect part. The layer of filter material is configured such that a product of the thickness of the layer of filter material and the imaginary part of the refractive index of the layer of filter material is above 1 nm.

Abstract translation: 集成电路包括衬底和衬底上方的互连部分，并且还包括衬底中的感光区域。 提供与感光区域对准的过滤器。 过滤器由至少一层过滤材料形成。 在用于前侧照明的一个实施例中，过滤材料层位于互连部分和基板之间的感光区域上方。 在背面照明的另一实施方案中，过滤材料层位于与互连部分相对的光敏区域的下方。 过滤材料层被配置为使得过滤材料层的厚度和过滤材料层的折射率的虚部的乘积高于1nm。

公开(公告)号：US09182474B2

公开(公告)日：2015-11-10

申请号：US13768707

申请日：2013-02-15

Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Thierry Michel ,  Bruno Paille

IPC: G01S1/24 ,  G01S5/14 ,  G01S5/02 ,  G01S5/06 ,  H04B1/707

CPC classification number: G01S5/14 ,  G01S5/0221 ,  G01S5/06 ,  H04B1/707

Abstract: A method for localizing an object, including the acts of: transmission of a first signal by a first transmitter assigned to the object and of a second signal by at least one second transmitter; reception of the first and of the second signal by at least three receivers; in each receiver and for the first and the second signal: a) generation of a first and of a second reference signal; b) correlation between the first signal and the first reference signal and between the second signal and the second reference signal; c) interpolation of samples resulting from the correlation; d) deduction of the propagation time of the first and of the second signal; e) calculation of the difference between the propagation times of the first and of the second signal; and, by triangulation, deduction of the position of the object.

Abstract translation: 一种用于定位对象的方法，包括以下动作：由分配给对象的第一发射机传输第一信号，以及由至少一个第二发射机传输第二信号; 由至少三个接收器接收第一和第二信号; 在每个接收机中以及对于第一和第二信号：a）产生第一和第二参考信号; b）第一信号和第一参考信号之间以及第二信号和第二参考信号之间的相关; c）由相关产生的样本的插值; d）扣除第一和第二信号的传播时间; e）计算第一和第二信号的传播时间之差; 并通过三角测量来扣除物体的位置。

公开(公告)号：US09176009B2

公开(公告)日：2015-11-03

申请号：US14024481

申请日：2013-09-11

Applicant: STMicroelectronics SA

Inventor： Hani Sherry ,  Andreia Cathelin ,  Andreas Kaiser ,  Ullrich Pfeiffer ,  Janusz Grzyb ,  Yan Zhao

IPC: G01J5/02 ,  G01J5/10 ,  G01N21/3581 ,  G01J5/20 ,  H01Q23/00 ,  G01J5/00

CPC classification number: G01J5/22 ,  G01J5/10 ,  G01J5/20 ,  G01J2005/0077 ,  G01J2005/202 ,  G01N21/3581 ,  H01Q23/00 ,  Y10T29/49018

Abstract: A terahertz imager includes an array of pixel circuits. Each pixel circuit has an antenna and a detector. The detector is coupled to differential output terminals of the antenna. A frequency oscillator is configured to generate a frequency signal on an output line. The output line is coupled to an input terminal of the antenna of at least one of the pixel circuits.

Abstract translation: 太赫兹成像器包括像素电路阵列。 每个像素电路具有天线和检测器。 检测器耦合到天线的差分输出端。 频率振荡器被配置为在输出线上产生频率信号。 输出线耦合到至少一个像素电路的天线的输入端。

公开(公告)号：US09171973B2

公开(公告)日：2015-10-27

申请号：US14559006

申请日：2014-12-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat a l'Energie Atomique et aux Energies Alternatives

Inventor： Romain Girard Desprolet ,  Sandrine Lhostis ,  Salim Boutami ,  Michel Marty

IPC: H01L31/0232 ,  H01L31/0216 ,  G02B5/20 ,  H01L27/146

CPC classification number: H01L31/02162 ,  G02B5/203 ,  H01L27/14621 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02165 ,  H01L31/02327

Abstract: An integrated imaging device supports front face illumination with one or more photosensitive regions formed in a substrate. A lower dielectric region is provided over the substrate, the lower dielectric region having an upper face. A metal optical filter having a metal pattern is provided on the upper face (or extending into the lower dielectric region from the upper face). An upper dielectric region is provided on top of the lower dielectric region and metal optical filter. The lower dielectric region is at least part of a pre-metal dielectric layer, and the upper dielectric region is at least part of a metallization layer.

Abstract translation: 集成成像装置支持在基板中形成的一个或多个感光区域的前面照明。 下部电介质区域设置在衬底上，下部电介质区域具有上表面。 具有金属图案的金属滤光器设置在上表面（或从上表面延伸到下介电区域中）。 在下部电介质区域和金属光学滤波器的顶部设置有上部电介质区域。 下电介质区域是预金属介电层的至少一部分，并且上电介质区域是金属化层的至少一部分。

公开(公告)号：US09165943B2

公开(公告)日：2015-10-20

申请号：US13932371

申请日：2013-07-01

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/12 ,  H01L27/02 ,  H01L27/06

CPC classification number: H01L27/1203 ,  H01L27/0262 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207

Abstract: An integrated circuit includes an UTBOX insulating layer under and plumb with first and second electronic components, and corresponding ground planes and oppositely-doped wells made plumb with them. The wells contact with corresponding ground planes. A pair of oppositely doped bias electrodes, suitable for connecting corresponding bias voltages, contacts respective wells and ground planes. A third electrode contacts the first well. A first trench isolates one bias electrode from the third electrode and extends through the layer and into the first well. A second trench isolates the first bias electrode from one component. This trench has an extent that falls short of reaching an interface between the first ground plane and the first well.

Abstract translation: 集成电路包括在第一和第二电子部件下面并且铅垂的UTBOX绝缘层，以及相应的接地平面和与其相反的相对掺杂的阱。 油井与相应的地面接触。 一对相对掺杂的偏置电极适于连接相应的偏置电压，接触相应的阱和接地层。 第三电极接触第一阱。 第一沟槽将一个偏置电极与第三电极隔离并延伸穿过该层并进入第一阱。 第二沟槽将第一偏置电极与一个部件隔离。 该沟槽的程度不足以达到第一接地层与第一井之间的界面。

公开(公告)号：US09147695B2

公开(公告)日：2015-09-29

申请号：US14096509

申请日：2013-12-04

Applicant: STMICROELECTRONICS SA

Inventor： Frédéric Hasbani ,  Eric Remond

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/78648

Abstract: An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage.

Abstract translation: 集成单元可以包括nMOS晶体管和pMOS晶体管。 电池可以在完全耗尽的绝缘体上的技术中制造，并且可以以相同的可调偏置电压来偏置电池的晶体管的衬底。

公开(公告)号：US20150270447A1

公开(公告)日：2015-09-24

申请号：US14659751

申请日：2015-03-17

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie et aux Energies Alternatives

Inventor： Laurent Frey ,  Michel Marty

IPC: H01L33/44 ,  H01L21/66 ,  H01L33/62 ,  H01L33/00 ,  H01L33/34

CPC classification number: H01L33/44 ,  G02B1/11 ,  G02B1/113 ,  H01L22/26 ,  H01L27/1462 ,  H01L27/14649 ,  H01L27/14669 ,  H01L31/02161 ,  H01L31/02165 ,  H01L33/0054 ,  H01L33/34 ,  H01L33/62 ,  H01L2933/0025 ,  H01L2933/0066

Abstract: A photodiode has an active portion formed in a silicon substrate and covered with a stack of insulating layers successively including at least one first silicon oxide layer, an antireflection layer, and a second silicon oxide layer. The quantum efficiency of the photodiode is optimized by: determining, for the infrared wavelength, first thicknesses of the second layer corresponding to maximum absorptions of the photodiode, and selecting, from among the first thicknesses, a desired thickness, eoxD, so that a maximum manufacturing dispersion is smaller than a half of a pseudo-period separating two successive maximum absorption values.

Abstract translation: 光电二极管具有形成在硅衬底中的有源部分，并且被一层绝缘层覆盖，所述绝缘层依次包括至少一个第一氧化硅层，抗反射层和第二氧化硅层。 通过以下方式优化光电二极管的量子效率：对于红外波长，确定对应于光电二极管的最大吸收的第二层的第一厚度，并且从第一厚度中选择希望的厚度eoxD，使得最大值 制造色散小于分离两个连续最大吸收值的假周期的一半。

公开(公告)号：US20150270192A1

公开(公告)日：2015-09-24

申请号：US14659680

申请日：2015-03-17

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Pierre Bar ,  Alisee Taluy ,  Olga Kokshagina

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L21/3213 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76897 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14519 ,  H01L2224/29013 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/3015 ,  H01L2224/30519 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83801 ,  H01L2224/9211 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract translation: 一种装置包括组装在插入器上的芯片。 电绝缘层在芯片周围涂覆插入件的上表面。 第一金属线在插入件的上表面上延伸并且布置在与芯片连接的导电元件之间。 每个第一金属线的端部被布置成延伸超过芯片在插入件上的投影。 导热通孔将第一金属线的端部连接到支撑在设备的上表面处的散热器。