公开(公告)号：US10175192B2

公开(公告)日：2019-01-08

申请号：US15615414

申请日：2017-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ali Afzali-Ardakani ,  Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: G01N27/414 ,  G01N27/30 ,  H01L29/417 ,  H01L29/06 ,  H01L29/20 ,  H01L29/16 ,  G01N27/327

Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.

公开(公告)号：US10170660B2

公开(公告)日：2019-01-01

申请号：US14978469

申请日：2015-12-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: H01L31/028 ,  H01L31/18 ,  H01L31/0747 ,  H01L31/0352 ,  H01L31/036 ,  H01L31/0745

Abstract: A photovoltaic device includes a digital alloy buffer layer including a plurality of alternating layers of semiconductor material. An absorption layer epitaxially is grown on the digital alloy buffer layer, an intrinsic layer is formed on the absorption layer and a doped layer is formed on the intrinsic layer. A conductive contact is formed on the doped layer.

公开(公告)号：US20180374916A1

公开(公告)日：2018-12-27

申请号：US16119078

申请日：2018-08-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/90 ,  H01L27/0629

Abstract: A method for forming a capacitive device comprises forming a first dielectric layer on a substrate. Portions of the first dielectric layer are removed to for form a cavity in the first dielectric layer. A first layer of conductive material is deposited on the first dielectric layer and conformally along sidewalls of the cavity. The method further includes depositing a second dielectric layer on the first layer of conductive material, and depositing a second layer of conductive material on the second dielectric layer to form a capacitive device.

公开(公告)号：US10164092B2

公开(公告)日：2018-12-25

申请号：US15843644

申请日：2017-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L29/08 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/51

Abstract: A vertical field effect transistor includes a first source/drain region formed on or in a substrate. A tapered fin is formed a vertical device channel and has a first end portion attached to the first source/drain region. A second source/drain region is formed on a second end portion of the tapered fin. A gate structure surrounds the tapered fin.

公开(公告)号：US10147741B2

公开(公告)日：2018-12-04

申请号：US15342318

申请日：2016-11-03

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/04 ,  H01L29/08 ,  H01L29/06 ,  H01L21/84 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762

Abstract: A semiconductor structure including a multi-faceted epitaxial semiconductor structure within both a source region and a drain region and on exposed surfaces of a semiconductor fin is provided. The multi-faceted epitaxial semiconductor structure includes faceted epitaxial semiconductor material portions located on different portions of each vertical sidewall of the semiconductor fin and a topmost faceted epitaxial semiconductor material portion that is located on an exposed topmost horizontal surface of the semiconductor fin. The multi-faceted epitaxial semiconductor structure has increased surface area and thus an improvement in contact resistance can be obtained utilizing the same.

公开(公告)号：US10134831B2

公开(公告)日：2018-11-20

申请号：US15067794

申请日：2016-03-11

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L49/02 ,  H01L27/06

Abstract: A method for forming a capacitive device comprises forming a first dielectric layer on a substrate. Portions of the first dielectric layer are removed to for form a cavity in the first dielectric layer. A first layer of conductive material is deposited on the first dielectric layer and conformally along sidewalls of the cavity. The method further includes depositing a second dielectric layer on the first layer of conductive material, and depositing a second layer of conductive material on the second dielectric layer to form a capacitive device.

公开(公告)号：US20180331215A1

公开(公告)日：2018-11-15

申请号：US16031325

申请日：2018-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L21/31111 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66666

Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.

公开(公告)号：US20180269197A1

公开(公告)日：2018-09-20

申请号：US15463795

申请日：2017-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Jeng-Bang Yau

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/861 ,  H01L29/78

Abstract: An electric static discharge (ESD) diode pair is disclosed. The first diode of the device includes a first diode junction portion having vertically orientated and horizontally oriented portions of a first conductivity and a second diode junction portion of a second conductivity in direct contact with both of the vertically orientated and horizontally orientated portions of the first diode junction portion. The second diode of the device includes a first diode junction portion having vertically orientated and horizontally oriented portions of a second conductivity and a second diode junction portion having a first conductivity in direct contact with both of the vertically orientated and horizontally orientated portions of the first diode junction portion. A common electrical contact is in direct contact first diode junction portion for each of the first diode and the second diode.

公开(公告)号：US10079288B2

公开(公告)日：2018-09-18

申请号：US15175694

申请日：2016-06-07

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/16 ,  H01L29/24 ,  H01L21/30 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3065

CPC classification number: H01L29/4941 ,  H01L21/02271 ,  H01L21/02592 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/3003 ,  H01L21/3065 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/16 ,  H01L29/24 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66575

Abstract: A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.

公开(公告)号：US20180261630A1

公开(公告)日：2018-09-13

申请号：US15980197

申请日：2018-05-15

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/04 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/84 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure including a multi-faceted epitaxial semiconductor structure within both a source region and a drain region and on exposed surfaces of a semiconductor fin is provided. The multi-faceted epitaxial semiconductor structure includes faceted epitaxial semiconductor material portions located on different portions of each vertical sidewall of the semiconductor fin and a topmost faceted epitaxial semiconductor material portion that is located on an exposed topmost horizontal surface of the semiconductor fin. The multi-faceted epitaxial semiconductor structure has increased surface area and thus an improvement in contact resistance can be obtained utilizing the same.