公开(公告)号：US20160293239A1

公开(公告)日：2016-10-06

申请号：US15090399

申请日：2016-04-04

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Catherine Chen ,  Scott C. Best ,  John Eric Linstadt ,  Frederick A. Ware

IPC: G11C8/08 ,  G11C29/44 ,  G06F11/07 ,  G11C8/06

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0772 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

Abstract translation: 在系统初始化期间，存储器模块上的每个数据缓冲设备和/或存储器设备被配置为唯一（至少对于模块）设备标识号。 为了访问单个设备（而不是多个缓冲器和/或存储设备），使用分别连接到所有数据缓冲设备或存储设备的命令总线将目标识别号码写入所有设备。 各个设备标识号与目标识别号码不一致的设备被配置为忽略未来的命令总线事务（至少直到调试模式被关闭）。所选择的设备被配置有与目标识别号码相匹配的设备标识号 被配置为响应命令总线事务。

公开(公告)号：US20160275033A1

公开(公告)日：2016-09-22

申请号：US15169275

申请日：2016-05-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kishore Kasamsetty

IPC: G06F13/40 ,  G11C5/02 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0683 ,  G06F12/00 ,  G06F12/02 ,  G06F13/1657 ,  G06F13/1668 ,  G06F13/4282 ,  G11C5/02

Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.

Abstract translation: 多芯片封装包括形成有多个存储器控制器电路的逻辑集成电路（IC）管芯，第一存储器IC管芯和第二存储器IC管芯。 第二存储器IC管芯安装到第一存储器IC管芯。 第一存储器IC管芯和逻辑IC管芯彼此安装。 逻辑IC芯片包括用于耦合到多个串行链路的串行链路接口。 第一存储器管芯包括由多个存储器控制器电路中的第一个访问的第一存储器组和由多个存储器控制器电路中的第二存储器控制器电路访问的第二存储器组。

公开(公告)号：US20160260469A1

公开(公告)日：2016-09-08

申请号：US15155794

申请日：2016-05-16

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4072

CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

公开(公告)号：US09437279B2

公开(公告)日：2016-09-06

申请号：US14951190

申请日：2015-11-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/22 ,  G11C11/4076 ,  G06F13/16 ,  G06F13/42 ,  G11C8/18 ,  G11C7/10 ,  G06F1/10 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

Abstract translation: 时钟信号通过时钟信号线发送到第一和第二集成电路（IC）组件，该时钟信号在第一IC组件处具有第一到达时间，而在第二IC组件处具有第二较晚的到达时间。 在对应于时钟信号的转变的各个时刻，写入命令被发送到要被这些分量采样的第一和第二IC组件，并且与写命令相关联地将写数据发送到第一和第二IC组件。 第一和第二选通信号分别被发送到第一和第二IC组件，以便在这些组件中对第一和第二写入数据进行时间接收。 从多个相位偏移定时信号中选择第一和第二选通信号，以补偿时钟信号与第一和第二选通信号之间的各自的定时偏差。

公开(公告)号：US09437276B2

公开(公告)日：2016-09-06

申请号：US15132017

申请日：2016-04-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F12/00 ,  G06F13/00 ,  G11C11/406 ,  G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1636 ,  G06F13/1689 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4061

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US20160231963A1

公开(公告)日：2016-08-11

申请号：US15132017

申请日：2016-04-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1636 ,  G06F13/1689 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4061

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US20160231962A1

公开(公告)日：2016-08-11

申请号：US15022176

申请日：2014-09-23

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2207/107

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

Abstract translation: 存储器组件包括存储器组和用于接收读取 - 修改 - 写入命令的命令接口，其具有指示存储器组中的位置的相关联的读取地址，以及从读取的指示的存储器组中的位置访问读取数据 从接收到读 - 修改 - 写入命令的时间开始，或者与多个读 - 修改 - 写入命令重叠，可调节延迟时间之后的地址。 存储器组件还包括用于接收与读取 - 修改 - 写入命令相关联的写入数据的数据接口和用于将接收到的写入数据与读取的数据合并以形成合并数据的纠错电路，并将合并的数据写入到 由读取地址指示的存储体。

公开(公告)号：US09367248B2

公开(公告)日：2016-06-14

申请号：US14745746

申请日：2015-06-22

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: H04L7/033 ,  G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4078 ,  G06F12/02 ,  G11C11/406 ,  G11C21/00 ,  H04L7/00

CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

公开(公告)号：US20160056842A1

公开(公告)日：2016-02-25

申请号：US14814206

申请日：2015-07-30

Applicant: Rambus Inc.

Inventor： John Eric Linstadt ,  Frederick A. Ware

IPC: H03M13/15 ,  H03M13/09 ,  G06F11/10

CPC classification number: H04L1/0047 ,  G06F11/1004 ,  H03M13/1515 ,  H03M13/1575 ,  H03M13/19

Abstract: A status encoder generates a checksum that encodes a status condition together with the checksum of an associated message. A receiver determines an inverse transformation that when applied to the received status-encoded checksum recovers the parity information associated with the codeword. The status condition can then be recovered based on the selection of the inverse transformation that correctly recovers the parity information from the status-encoded checksum. Beneficially, the status condition can be encoded without requiring additional signal lines or lengthening the codeword relative to conventional error correction devices.

Abstract translation: 状态编码器生成校验和，其将状态条件与相关消息的校验和一起编码。 接收机确定当应用于接收到的状态编码校验和时恢复与码字相关联的奇偶校验信息的逆变换。 然后可以基于从状态编码的校验和正确地恢复奇偶校验信息的逆变换的选择来恢复状态条件。 有利的是，可以编码状态条件，而不需要额外的信号线或相对于传统的纠错装置来延长码字。

公开(公告)号：US09262269B2

公开(公告)日：2016-02-16

申请号：US14836467

申请日：2015-08-26

Applicant: Rambus Inc.

Inventor： Yuanlong Wang ,  Frederick A. Ware

IPC: G11C29/00 ,  G06F11/00 ,  G06F11/14 ,  H03M13/29 ,  G06F11/10

CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract translation: 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。