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121.
公开(公告)号:US10276619B2
公开(公告)日:2019-04-30
申请号:US15921032
申请日:2018-03-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Hsun-Ying Huang
IPC: H01L27/146 , H01L23/48
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.
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公开(公告)号:US20190043912A1
公开(公告)日:2019-02-07
申请号:US16148141
申请日:2018-10-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chun-Chieh Chuang , Dun-Nian Yaung , Jen-Cheng Liu , Tzu-Hsuan Hsu , Feng-Chi Hung , Min-Feng Kao
IPC: H01L27/146
CPC classification number: H01L27/14636 , H01L27/14603 , H01L27/1463 , H01L27/14632 , H01L27/14634 , H01L27/1464 , H01L27/14687 , H01L27/1469
Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.
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公开(公告)号:US10163951B2
公开(公告)日:2018-12-25
申请号:US15170200
申请日:2016-06-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Szu-Ying Chen , Min-Feng Kao , Jen-Cheng Liu , Feng-Chi Hung , Dun-Nian Yaung
IPC: H01L27/146
Abstract: In some embodiments, the present disclosure relates to an image sensor device. The image sensor device has an isolation well region surrounding a photodetector arranged within a substrate at a first depth. A gate stack is arranged over the isolation well region along a first surface of the substrate. The gate stack defines an edge. A doped isolation feature is arranged within the substrate at a second depth between the isolation well region and the gate stack. The gate stack is vertically over an active area. The doped isolation feature extends from the edge of the gate stack to under the gate stack.
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公开(公告)号:US10121812B2
公开(公告)日:2018-11-06
申请号:US15365064
申请日:2016-11-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jeng-Shyan Lin , Dun-Nian Yaung , Jen-Cheng Liu , Hsun-Ying Huang , Wei-Chih Weng , Yu-Yang Shen
IPC: H01L21/78 , H01L27/146 , H01L23/528 , H01L25/065 , H01L25/00 , H01L23/48 , H01L23/532
Abstract: The present disclosure relates to a method of forming a multi-dimensional integrated chip having tiers connected in a front-to-back configuration, and an associated apparatus. In some embodiments, the method is performed by forming one or more semiconductor devices within a first substrate, forming one or more image sensing elements within a second substrate, and bonding a first dielectric structure over the first substrate to a back-side of the second substrate by way of a bonding structure. An inter-tier interconnect structure, comprising a plurality of different segments, respectively having sidewalls with different sidewall angles, is formed to extend through the bonding structure and the second substrate. The inter-tier interconnect structure is configured to electrically couple a first metal interconnect layer over the first substrate to a second metal interconnect layer over the second substrate.
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公开(公告)号:US20170221952A1
公开(公告)日:2017-08-03
申请号:US15487473
申请日:2017-04-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Kuo-Chin Huang , Pao-Tung Chen , Wei-Chieh Chiang , Kazuaki Hashimoto , Jen-Cheng Liu
IPC: H01L27/146
CPC classification number: H01L27/14636 , H01L27/14618 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14683 , H01L27/14685 , H01L27/1469
Abstract: An image sensor chip having a sidewall interconnect structure to bond and/or electrically couple the image sensor chip to a package substrate is provided. The image sensor chip includes a substrate supporting an integrated circuit (IC) configured to sense incident light. The sidewall interconnect structure is arranged along a sidewall of the substrate and electrically coupled with the IC. A method for manufacturing the image sensor chip and an image sensor package including the image sensor chip are also provided.
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公开(公告)号:US20170186799A1
公开(公告)日:2017-06-29
申请号:US15365064
申请日:2016-11-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jeng-Shyan Lin , Dun-Nian Yaung , Jen-Cheng Liu , Hsun-Ying Huang , Wei-Chih Weng , Yu-Yang Shen
IPC: H01L27/146 , H01L25/00 , H01L25/065 , H01L23/528 , H01L21/78
CPC classification number: H01L27/14634 , H01L21/76898 , H01L21/78 , H01L23/481 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L25/0657 , H01L25/50 , H01L27/1463 , H01L27/14636 , H01L27/1469
Abstract: The present disclosure relates to a method of forming a multi-dimensional integrated chip having tiers connected in a front-to-back configuration, and an associated apparatus. In some embodiments, the method is performed by forming one or more semiconductor devices within a first substrate, forming one or more image sensing elements within a second substrate, and bonding a first dielectric structure over the first substrate to a back-side of the second substrate by way of a bonding structure. An inter-tier interconnect structure, comprising a plurality of different segments, respectively having sidewalls with different sidewall angles, is formed to extend through the bonding structure and the second substrate. The inter-tier interconnect structure is configured to electrically couple a first metal interconnect layer over the first substrate to a second metal interconnect layer over the second substrate.
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公开(公告)号:US20170154850A1
公开(公告)日:2017-06-01
申请号:US15143950
申请日:2016-05-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Hsun-Ying Huang
IPC: H01L23/538 , H01L21/768 , H01L23/31 , H01L23/528 , H01L23/00
CPC classification number: H01L23/5384 , H01L21/6835 , H01L21/76804 , H01L21/76832 , H01L21/76883 , H01L21/76898 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L23/481 , H01L23/522 , H01L23/525 , H01L23/5283 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2221/68327 , H01L2221/6834 , H01L2224/02313 , H01L2224/02372 , H01L2224/0239 , H01L2224/03002 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05073 , H01L2224/05082 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/11002 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13183 , H01L2224/16227 , H01L2224/16245 , H01L2224/81005 , H01L2224/81815 , H01L2924/01013 , H01L2924/00014 , H01L2924/014 , H01L2924/01047
Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) having a back-side through-silicon-via (BTSV) with a direct physical connection between a metal interconnect layer and a back-side conductive bond pad. The IC has metal interconnect layers arranged within an inter-level dielectric structure disposed onto a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate, and a conductive bond pad is arranged over the dielectric layer. A BTSV extends from one of the metal interconnect layers through the substrate and the dielectric layer to the conductive bond pad. A conductive bump is arranged onto the conductive bond pad, which has a substantially planar lower surface extending from over the BTSV to below the conductive bump. Directly connecting the conductive bond pad to the BTSV reduces a size of the conductive bond thereby improving a routing capability of the conductive bond pad.
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公开(公告)号:US09634053B2
公开(公告)日:2017-04-25
申请号:US14564231
申请日:2014-12-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Kuo-Chin Huang , Pao-Tung Chen , Wei-Chieh Chiang , Kazuaki Hashimoto , Jen-Cheng Liu
IPC: H01L27/146
CPC classification number: H01L27/14636 , H01L27/14618 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14683 , H01L27/14685 , H01L27/1469
Abstract: An image sensor chip having a sidewall interconnect structure to bond and/or electrically couple the image sensor chip to a package substrate is provided. The image sensor chip includes a substrate supporting an integrated circuit (IC) configured to sense incident light. The sidewall interconnect structure is arranged along a sidewall of the substrate and electrically coupled with the IC. A method for manufacturing the image sensor chip and an image sensor package including the image sensor chip are also provided.
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公开(公告)号:US09536915B2
公开(公告)日:2017-01-03
申请号:US15147888
申请日:2016-05-05
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Keng-Yu Chou , Kazuaki Hashimoto , Jen-Cheng Liu , Jhy-Jyi Sze , Wei-Chieh Chiang , Pao-Tung Chen
IPC: H04N5/33 , H01L27/146 , H04N5/335 , G02B1/11 , H04N9/04 , G02B5/20 , G02B5/28 , G02B27/10 , G02B27/12 , H04N5/225
CPC classification number: H01L27/14621 , G02B1/11 , G02B5/201 , G02B5/208 , G02B5/22 , G02B5/282 , G02B27/1013 , G02B27/123 , H01L27/1462 , H01L27/14627 , H01L27/14629 , H01L27/14645 , H01L27/14649 , H01L27/14685 , H04N5/2253 , H04N5/2254 , H04N5/33 , H04N5/335 , H04N9/045 , H04N2209/042
Abstract: An image sensor includes a substrate, photosensitive devices, a color filter layer, a micro-lens layer and an infrared filter layer. The photosensitive devices are disposed in the substrate. The color filter layer is disposed to cover the photosensitive devices. The micro-lens layer is disposed on the color filter layer. The infrared filter layer directly covers the micro-lens layer.
Abstract translation: 图像传感器包括基板,感光装置,滤色器层,微透镜层和红外滤光层。 感光装置设置在基板中。 滤色器层设置成覆盖感光装置。 微透镜层设置在滤色器层上。 红外滤光层直接覆盖微透镜层。
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公开(公告)号:US20160276382A1
公开(公告)日:2016-09-22
申请号:US15170200
申请日:2016-06-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Szu-Ying Chen , Min-Feng Kao , Jen-Cheng Liu , Feng-Chi Hung , Dun-Nian Yaung
IPC: H01L27/146
CPC classification number: H01L27/1463 , H01L27/14612 , H01L27/14614 , H01L27/14636 , H01L27/1464 , H01L27/14643 , H01L27/14645 , H01L27/14689
Abstract: In some embodiments, the present disclosure relates to an image sensor device. The image sensor device has an isolation well region surrounding a photodetector arranged within a substrate at a first depth. A gate stack is arranged over the isolation well region along a first surface of the substrate. The gate stack defines an edge. A doped isolation feature is arranged within the substrate at a second depth between the isolation well region and the gate stack. The gate stack is vertically over an active area. The doped isolation feature extends from the edge of the gate stack to under the gate stack.
Abstract translation: 在一些实施例中,本公开涉及一种图像传感器装置。 图像传感器装置具有围绕设置在第一深度的衬底内的光电检测器的隔离阱区域。 栅极堆叠沿着衬底的第一表面布置在隔离阱区域的上方。 门堆栈定义一个边。 在隔离阱区域和栅极堆叠之间的第二深度处,在衬底内布置掺杂隔离特征。 栅极堆栈垂直于有效区域。 掺杂隔离特征从栅极堆叠的边缘延伸到栅极堆叠下方。
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