公开(公告)号：US07324258B2

公开(公告)日：2008-01-29

申请号：US11151217

申请日：2005-06-13

Applicant: Yong Hwan Kwon ,  Joong Seon Choe

Inventor： Yong Hwan Kwon ,  Joong Seon Choe

IPC: G02F1/03

CPC classification number: G02F1/025 ,  G02F1/0121 ,  G02F2201/063 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: Provided is a semiconductor optical modulator device in which a resistor for impedance matching is integrated in a device in order to improve performance and to reduce cost during the fabrication of an ultra high speed optical modulator module. A doped layer in an epitaxial layer of the optical modulator device is used as a resistor for impedance matching. According to this method, it is possible to more easily realize an optical device compared with optical device fabrication processes in which additional resistors are used in the outside and the inside of the device for impedance matching.

Abstract translation: 提供了一种半导体光调制器件，其中用于阻抗匹配的电阻器集成在器件中，以便在超高速光调制器模块的制造期间提高性能并降低成本。 光调制器件的外延层中的掺杂层用作阻抗匹配的电阻器。 根据该方法，与用于阻抗匹配的装置的外部和内部使用附加电阻器的光学器件制造工艺相比，可以更容易地实现光学器件。

公开(公告)号：US20070007664A1

公开(公告)日：2007-01-11

申请号：US11428169

申请日：2006-06-30

Applicant: Chung-Sun LEE ,  Yong-Hwan KWON ,  Kyoung-Sei CHOI ,  Woon-Byung KANG

Inventor： Chung-Sun LEE ,  Yong-Hwan KWON ,  Kyoung-Sei CHOI ,  Woon-Byung KANG

IPC: H01L23/48 ,  H01L21/00 ,  H01L21/44

CPC classification number: H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/562 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided are a semiconductor package having a semiconductor chip, a rear surface of which is molded, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip including a wafer and a metal pad formed on a front surface of the wafer; a solder ball formed on a front surface of the wafer, and electrically connected to the metal pad; and a reinforcing member formed on a rear surface of the wafer. The reinforcing member is formed of an epoxy molding compound, and the reinforcing member protrudes at least 5 μm from side surfaces of the semiconductor chip.

Abstract translation: 提供一种半导体封装，其具有半导体芯片，其后表面被模制，以及制造半导体封装的方法。 半导体封装包括：半导体芯片，包括晶片和形成在晶片前表面上的金属焊盘; 形成在所述晶片的前表面上并且电连接到所述金属焊盘的焊球; 以及形成在晶片的后表面上的加强构件。 加强构件由环氧树脂模塑料形成，并且加强构件从半导体芯片的侧表面突出至少5微米。

公开(公告)号：US20060071303A1

公开(公告)日：2006-04-06

申请号：US11218260

申请日：2005-08-31

Applicant: Chung-Sun Lee ,  Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Kyoung-Sei Choi

Inventor： Chung-Sun Lee ,  Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Kyoung-Sei Choi

IPC: H01L23/58

CPC classification number: H01L23/13 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/3025 ,  H05K1/0271 ,  H05K1/189 ,  H05K3/0038 ,  H05K3/027 ,  H05K3/22 ,  H05K2201/09072 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05099

Abstract: Embodiments of the present invention are directed to a film substrate of a semiconductor package. The film substrate of the semiconductor package comprises a thin film insulating substrate and a thin copper circuit pattern. An inter-pattern groove between the thin copper circuit patterns is formed by laser etching. Accordingly, the embodiment improves electrical contact between the film substrate and a semiconductor chip mounted thereon, and improves the manufacturing process for the film substrate by adopting a simple laser machining to form the thin copper circuit pattern in lieu of a traditional wet-etching process that undergoes complex lithography steps.

Abstract translation: 本发明的实施例涉及一种半导体封装的薄膜基片。 半导体封装的薄膜基板包括薄膜绝缘基板和薄铜电路图案。 通过激光蚀刻形成薄铜电路图案之间的图案间凹槽。 因此，本实施方式改善了薄膜基板与安装在其上的半导体芯片之间的电接触，并且通过采用简单的激光加工来形成薄铜电路图案来代替薄的基板的制造工艺来代替传统的湿式蚀刻工艺， 经历复杂的光刻步骤。

公开(公告)号：US20060003568A1

公开(公告)日：2006-01-05

申请号：US11086614

申请日：2005-03-21

Applicant: Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

Inventor： Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

IPC: H01L21/44

CPC classification number: H05K3/28 ,  H05K1/036 ,  H05K1/0393 ,  H05K3/101 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/0129 ,  H05K2201/0162 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/0759 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916

Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate fine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

Abstract translation: 根据本发明的制造带布线板的方法可以在形成布线图案中采用压印工艺，从而减少了用于制造带布线板的工艺的数量，并允许制造工艺在单个生产线中进行。 因此，制造时间和成本可能降低。 布线图案的轮廓可以通过模具的印模图案的形状来确定。 这可以建立内部和外部引线的顶部宽度并且结合细小的垫间距。 虽然ILB和OLB过程可能使用NCP，但是由于软和弹性布线图案可能建立连接可靠性。

公开(公告)号：US06607938B2

公开(公告)日：2003-08-19

申请号：US10200077

申请日：2002-07-18

Applicant: Yong Hwan Kwon ,  Sa Yoon Kang ,  Dong Hyeon Jang ,  Min Kyo Cho ,  Gu Sung Kim

Inventor： Yong Hwan Kwon ,  Sa Yoon Kang ,  Dong Hyeon Jang ,  Min Kyo Cho ,  Gu Sung Kim

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/013

Abstract: A wafer level chip package has a redistrubution substrate, at least one lower semiconductor chip stacked on the redisctribution substrate, and an uppermost semiconductor chip. The redistribution substrate has a redistribution layer and substrate pads connected to the redistribution layer. The lower semiconductor chip is stacked on the redistribution layer and may have through holes for partially exposing the redistribution layer, the through holes corresponding to the substrate pads, and having conductive filling material filling the through holes. The uppermost semiconductor chip may have the same elements as the lower semiconductor chip, and may be flip chip bonded to the through holes. The package may further have a filling layer for filling areas between chips, a metal lid for coating most of the external surfaces, and external connection terminals formed on and electrically connected to the exposed redistribution layer from the first dielectric layer of the redistribution substrate.