公开(公告)号：US10964665B2

公开(公告)日：2021-03-30

申请号：US15408930

申请日：2017-01-18

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： William Johnstone Ray ,  Richard Austin Blanchard ,  Mark David Lowenthal ,  Bradley Steven Oraw

IPC: H01L23/00 ,  H05K1/02 ,  H01L25/00 ,  H01L25/075 ,  H05K3/12 ,  H01L25/07 ,  H01L25/18 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L33/20

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

公开(公告)号：US20210050334A1

公开(公告)日：2021-02-18

申请号：US17089142

申请日：2020-11-04

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： William Johnstone Ray ,  Michael LeFebvre ,  Darin Wagner ,  Richard A. Blanchard

IPC: H01L25/075 ,  H01L25/065

Abstract: Over a flexible substrate are deposited stacked pixel layers including a bottom layer of LEDs forming blue pixels, a middle layer of LEDs forming green pixels, and a top layer of LEDs forming red pixels. Each LED die comprises an LED portion and an integrated transistor portion. Applying a voltage to a control terminal of the transistor portion energizes the LED portion. The pixels are substantially transparent, due to the LEDs being microscopic and the pixel areas being much larger, to allow light from the underlying layers to pass through. The three layers of pixels are aligned so that a combination of a single top red pixel, a single underlying green pixel, and a single underlying blue pixel form a single multi-color pixel. The different layers have transparent column and row lines.

公开(公告)号：US10192478B2

公开(公告)日：2019-01-29

申请号：US15350625

申请日：2016-11-14

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： Brian D. Ogonowsky

IPC: H01L21/00 ,  G09G3/32 ,  H01L33/06 ,  H01L33/32 ,  H01L33/40 ,  H01L33/00 ,  H01L33/48 ,  H01L33/62 ,  H01L33/58 ,  H01L33/54 ,  H01L33/50 ,  H01L25/075

Abstract: Pixel locations in an addressable display are defined by metal landings on a top surface of a flexible substrate, such as by depositing a metal film and etching the film. The substrate surface may be hydrophobic so that the hydrophobic surface is exposed between the metal landings. The substrate has conductive vias that connect the metal landings to traces on a bottom surface of the substrate for connection to addressing circuitry. LED ink is then blanket-printed over the top surface and cured to electrically connect bottom electrodes of the LEDs to the metal landings. LEDs that fall between the landings are ineffective. A dielectric layer is blanket-printed which exposes the top electrodes, and a transparent conductor layer is blanket-printed over the LEDs to connect all LEDs associated with an individual pixel location in parallel. Accordingly, all printed steps can be performed without any alignment.

公开(公告)号：US09913371B2

公开(公告)日：2018-03-06

申请号：US15405601

申请日：2017-01-13

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： William Johnstone Ray ,  Richard Austin Blanchard ,  Mark David Lowenthal ,  Bradley Steven Oraw

IPC: H05K1/00 ,  H05K1/02 ,  H01L25/07 ,  H01L25/075 ,  H01L25/18 ,  H01L25/00 ,  H01L33/20 ,  H05K1/18 ,  H05K7/00 ,  H01L21/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H05K1/0296 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/95 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/18 ,  H01L25/50 ,  H01L33/20 ,  H01L2221/68381 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/25105 ,  H01L2224/25174 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82143 ,  H01L2224/92244 ,  H01L2224/95085 ,  H01L2224/95101 ,  H01L2224/95102 ,  H01L2224/95115 ,  H01L2224/95143 ,  H01L2224/95146 ,  H01L2924/10253 ,  H01L2924/12 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/13 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

公开(公告)号：US09572249B2

公开(公告)日：2017-02-14

申请号：US14204800

申请日：2014-03-11

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： William Johnstone Ray ,  Richard Austin Blanchard ,  Mark David Lowenthal ,  Bradley Steven Oraw

IPC: H05K7/00 ,  H05K1/02 ,  H01L25/00 ,  H01L25/075 ,  H01L33/20 ,  H05K1/18 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/95 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/06 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/18 ,  H01L25/50 ,  H01L33/20 ,  H01L2221/68381 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/25105 ,  H01L2224/25174 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82143 ,  H01L2224/92244 ,  H01L2224/95085 ,  H01L2224/95101 ,  H01L2224/95102 ,  H01L2224/95115 ,  H01L2224/95143 ,  H01L2224/95146 ,  H01L2924/10253 ,  H01L2924/12 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/13 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H05K1/029 ,  H05K1/0296 ,  H05K3/12

Abstract: A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

Abstract translation: 可编程电路包括微阵列晶体管或二极管的印刷组阵列。 这些装置被预先形成并印刷成油墨并固化。 每个组中的设备并联连接，以使每个组充当单个设备。 在一个实施例中，每个组中包含约10个设备，因此冗余使得每个组非常可靠。 每个组具有终止于衬底上的贴片区域中的至少一个电引线。 互连导体图案将贴片区域中的组的至少一些引线互连以产生用于通用电路的定制应用的逻辑电路。 这些组也可以互连成逻辑门，并且栅极引线终止于贴片区域。 然后，互连导体图案将形成复合逻辑电路的栅极互连。

公开(公告)号：US09572222B2

公开(公告)日：2017-02-14

申请号：US14837934

申请日：2015-08-27

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： Bradley S. Oraw

IPC: H01L33/32 ,  H05B33/08 ,  H01L33/00 ,  H01L27/15 ,  H01L23/00

CPC classification number: H05B33/0857 ,  H01L24/24 ,  H01L24/82 ,  H01L27/15 ,  H01L33/0041 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12035 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H05B33/083 ,  H01L2924/00

Abstract: LED modules are disclosed having a control MOSFET, or other transistor, in series with an LED. In one embodiment, a MOSFET wafer is bonded to an LED wafer and singulated to form thousands of active 3-terminal LED modules with the same footprint as a single LED. Despite the different forward voltages of red, green, and blue LEDs, RGB modules may be connected in parallel and their control voltages staggered at 60 Hz or greater to generate a single perceived color, such as white. The RGB modules may be connected in a panel for general illumination or for a color display. A single dielectric layer in a panel may encapsulate all the RGB modules to form a compact and inexpensive panel. Various addressing techniques are described for both a color display and a lighting panel. Various circuits are described for reducing the sensitivity of the LED to variations in input voltage.

Abstract translation: 公开了具有与LED串联的控制MOSFET或其它晶体管的LED模块。 在一个实施例中，MOSFET晶片被结合到LED晶片并且被单片化以形成具有与单个LED相同的占空比的数千个有源3端子LED模块。 尽管红色，绿色和蓝色LED的正向电压不同，但是RGB模块可能并联连接，并且其控制电压以60Hz或更大的方式交错，以产生单个感知颜色，例如白色。 RGB模块可以连接在用于一般照明或彩色显示的面板中。 面板中的单个电介质层可以封装所有的RGB模块以形成紧凑且廉价的面板。 对于彩色显示器和照明面板都描述了各种寻址技术。 描述了各种电路，用于降低LED对输入电压变化的灵敏度。

公开(公告)号：US09548511B2

公开(公告)日：2017-01-17

申请号：US14745709

申请日：2015-06-22

Applicant: NTHDEGREE TECHNOLOGIES WORLDWIDE INC.

Inventor： Vera N. Lockett ,  John G. Gustafson ,  William J. Ray ,  Yasser Salah

IPC: H01M2/00 ,  H01M10/05 ,  C09D5/00 ,  H01G11/24 ,  H01G11/36 ,  H01G11/38 ,  H01G11/46 ,  H01G11/52 ,  H01M2/16 ,  H01M4/48 ,  H01M4/50 ,  H01M10/36 ,  H01M6/40 ,  H01M4/62

CPC classification number: H01M4/9016 ,  C09D5/00 ,  H01G11/24 ,  H01G11/36 ,  H01G11/38 ,  H01G11/46 ,  H01G11/52 ,  H01M2/1646 ,  H01M4/48 ,  H01M4/50 ,  H01M4/502 ,  H01M4/625 ,  H01M6/40 ,  H01M8/16 ,  H01M10/05 ,  H01M10/36 ,  Y02E60/13

Abstract: An energy storage device can include a cathode having a first plurality of frustules, where the first plurality of frustules can include nanostructures having an oxide of manganese. The energy storage device can include an anode comprising a second plurality of frustules, where the second plurality of frustules can include nanostructures having zinc oxide. A frustule can have a plurality of nanostructures on at least one surface, where the plurality of nanostructures can include an oxide of manganese. A frustule can have a plurality of nanostructures on at least one surface, where the plurality of nanostructures can include zinc oxide. An electrode for an energy storage device includes a plurality of frustules, where each of the plurality of frustules can have a plurality of nanostructures formed on at least one surface.

Abstract translation: 能量存储装置可以包括具有第一多个截头圆锥体的阴极，其中第一多个截头体可以包括具有锰氧化物的纳米结构。 能量存储装置可以包括包括第二多个截头圆锥的阳极，其中第二多个截头体可以包括具有氧化锌的纳米结构。 截头锥体可以在至少一个表面上具有多个纳米结构，其中多个纳米结构可以包括锰的氧化物。 截头圆锥体可以在至少一个表面上具有多个纳米结构，其中多个纳米结构可以包括氧化锌。 用于能量存储装置的电极包括多个截头圆锥体，其中所述多个截头圆锥体中的每一个可以具有形成在至少一个表面上的多个纳米结构。

公开(公告)号：US09526148B2

公开(公告)日：2016-12-20

申请号：US14831351

申请日：2015-08-20

Applicant: NthDegree Technologies Worldwide Inc.

Inventor： Mark David Lowenthal ,  William Johnstone Ray ,  Peter Michael Bray ,  David R. Bowden

IPC: G09F9/37 ,  H05B37/02 ,  G09G3/14 ,  H05B33/08 ,  H05B41/24 ,  A47F3/00 ,  G09F13/00 ,  H01F38/14 ,  H02J5/00

CPC classification number: G09F9/37 ,  A47F3/001 ,  G09F13/00 ,  G09G3/14 ,  G09G2330/028 ,  H01F38/14 ,  H02J5/005 ,  H02J7/025 ,  H02J50/12 ,  H05B33/0815 ,  H05B37/0209 ,  H05B37/0227 ,  H05B41/245

Abstract: An exemplary system comprises a power regulator and an emitting apparatus. The emitting apparatus is typically attached to or integrated with a display object, such as a merchandise package or container. A support structure, such as a point of purchase display, typically contains or supports one or more power regulators and display objects. The power regulator comprises a controller and a primary inductor, and the controller is adapted to provide a voltage or current to the primary inductor to generate a first primary inductor voltage. The emitting apparatus comprises an illumination source and a secondary inductor coupled to the illumination source. The illumination source is adapted to emit visible light when the power regulator is in an on state and when the secondary inductor is within a predetermined distance of the primary inductor. In exemplary embodiments, the first and second inductors are substantially planar.

公开(公告)号：US09525097B2

公开(公告)日：2016-12-20

申请号：US14214559

申请日：2014-03-14

Applicant: Nthdegree Technologies Worldwide Inc.

Inventor： Tricia Youngbull ,  Bradley Steven Oraw ,  William Johnstone Ray

IPC: H01L27/142 ,  H01L31/0352 ,  H01L31/18 ,  H01L31/0465 ,  H01L31/0463 ,  H01L31/046

CPC classification number: H01L31/1824 ,  H01L27/1421 ,  H01L31/035281 ,  H01L31/03529 ,  H01L31/0443 ,  H01L31/046 ,  H01L31/0463 ,  H01L31/0465 ,  H01L31/18 ,  H01L31/188 ,  Y02E10/50

Abstract: A PV module is formed having an array of PV cells, where the cells are separated by gaps. Each cell contains an array of small silicon sphere diodes (10-300 microns in diameter) connected in parallel. The diodes and conductor layers may be patterned by printing. A continuous metal substrate supports the diodes and conductor layers in all the cells. A dielectric substrate is laminated to the metal substrate. Trenches are then formed by laser ablation around the cells to sever the metal substrate to form electrically isolated PV cells. A metallization step is then performed to connect the cells in series to increase the voltage output of the PV module. An electrically isolated bypass diode for each cell is also formed by the trenching step. The metallization step connects the bypass diode and its associated cell in a reverse-parallel relationship.

Abstract translation: 形成具有PV电池阵列的PV模块，其中电池被间隙分开。 每个电池都包含并联连接的小硅球二极管阵列（直径10-300微米）。 可以通过印刷将二极管和导体层图案化。 连续的金属基板在所有单元中支撑二极管和导体层。 将电介质基板层压到金属基板上。 然后通过在细胞周围的激光烧蚀形成沟槽以切断金属基底以形成电隔离的PV电池。 然后执行金属化步骤以串联连接电池，以增加PV模块的电压输出。 用于每个电池的电隔离旁路二极管也通过开沟步骤形成。 金属化步骤以反平行关系连接旁路二极管及其相关联的电池。

公开(公告)号：US09504099B2

公开(公告)日：2016-11-22

申请号：US14063006

申请日：2013-10-25

Applicant: NthDegree Technologies Worldwide Inc.

Inventor： Kenneth Stephen McGuire ,  Mark John Steinhardt ,  Corey Michael Bischoff ,  Edward Mack Sawicki ,  Erik John Hasenoehrl

IPC: H05B37/02 ,  H05B33/08

CPC classification number: H05B33/08 ,  H05B33/0857 ,  H05B37/0272 ,  Y02B20/48

Abstract: A light bulb base includes a power source interface configured to couple the light bulb base to a light bulb socket. It also includes a bulb-coupling interface configured to removably couple the light bulb base to a bulb assembly. A user interface mechanism is also included in the light bulb base, and is operable to control a function of the bulb assembly or the base when the base is coupled to the bulb assembly. The light bulb base may also include a receiver for receiving a signal from a remote control source and/or a controller configured to perform the function.

Abstract translation: 灯泡基座包括被配置为将灯泡基座耦合到灯泡插座的电源接口。 它还包括配置成可拆卸地将灯泡基座耦合到灯泡组件的灯泡耦合接口。 用户接口机构也包括在灯泡基座中，并且当基座联接到灯泡组件时可操作以控制灯泡组件或基座的功能。 灯泡基座还可以包括用于从远程控制源接收信号的接收器和/或被配置为执行该功能的控制器。