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    Metal-containing films as dielectric capping barrier for advanced interconnects
    153.
    发明授权
    Metal-containing films as dielectric capping barrier for advanced interconnects 有权
    含金属膜作为先进互连的电介质封盖屏障

    公开(公告)号：US09368448B2

    公开(公告)日：2016-06-14

    申请号：US14268727

    申请日：2014-05-02

    Applicant: Applied Materials, Inc.

    Inventor： Yihong Chen ,  Abhijit Basu Mallick ,  Mehul B. Naik ,  Srinivas D. Nemani

    IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528

    CPC classification number: H01L23/53238 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76879 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method is provided for forming an interconnect structure for use in semiconductor devices. The method starts with forming a low-k bulk dielectric layer on a substrate and then forming a trench in the low-k bulk dielectric layer. A liner layer is formed on the low-k bulk dielectric layer being deposited conformally to the trench. A copper layer is formed on the liner layer filling the trench. Portions of the copper layer and liner layer are removed to form an upper surface of the low-k bulk dielectric layer, the liner layer, and the copper layer. A metal containing dielectric layer is formed on the upper surface of the low-k bulk dielectric layer, the liner layer, and the copper layer.

    Abstract translation: 提供一种用于形成用于半导体器件的互连结构的方法。 该方法首先在衬底上形成低k体积电介质层，然后在低k体电介质层中形成沟槽。 衬底层形成在与沟槽共形沉积的低k体积电介质层上。 在填充沟槽的衬垫层上形成铜层。 去除部分铜层和衬层以形成低k体电介质层，衬里层和铜层的上表面。 在低k体电介质层，衬垫层和铜层的上表面上形成含金属的电介质层。

    Methods for silicon recess structures in a substrate by utilizing a doping layer
    155.
    发明授权
    Methods for silicon recess structures in a substrate by utilizing a doping layer 有权
    通过利用掺杂层在衬底中的硅凹陷结构的方法

    公开(公告)号：US09214377B2

    公开(公告)日：2015-12-15

    申请号：US14068312

    申请日：2013-10-31

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Ying Zhang ,  Hua Chung ,  Srinivas D. Nemani ,  Ludovic Godet

    IPC: H01L21/76 ,  H01L21/762 ,  H01L21/265

    CPC classification number: H01L21/76224 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/6831 ,  H01L29/66795

    Abstract: Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed.

    Abstract translation: 本发明的实施例提供了一种用于在具有良好的工艺控制的衬底中形成硅凹陷结构的方法，特别适用于制造用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠。 在一个实施例中，在衬底中形成凹陷结构的方法包括蚀刻由形成在衬底中的第二部分限定的衬底的第一部分，直到形成在衬底中的掺杂层露出。

    AIR GAP PROCESS
    156.
    发明申请
    AIR GAP PROCESS 有权
    空气过程

    公开(公告)号：US20150221541A1

    公开(公告)日：2015-08-06

    申请号：US14171400

    申请日：2014-02-03

    Applicant: APPLIED MATERIALS, INC.

    Inventor： Srinivas D. Nemani ,  Takehito Koshizawa

    IPC: H01L21/768 ,  H01L21/311

    CPC classification number: H01L21/7682 ,  H01J37/32357 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877

    Abstract: Methods are described for forming “air gaps” between adjacent metal lines on patterned substrates. The common name “air gap” will be used interchangeably with the more technically accurate “gas pocket” and both reflect a variety of pressures and elemental ratios. The air gaps are produced within narrow gaps between copper lines while wide gaps retain dielectric material. Retention of the dielectric material within the wide gaps enables formation of a desirable planar top surface. Using a hardmask layer and a selective dry-etch process enables a wet processing step to be avoided right before the formation of the air gaps. The air gaps can have a dielectric constant approaching one, favorably reducing interconnect capacitance compared with typical low-k dielectric materials.

    Abstract translation: 描述了在图案化基板上的相邻金属线之间形成“气隙”的方法。 通用名称“气隙”将与更技术上精确的“气囊”互换使用，并且都反映各种压力和元素比。 气隙在铜线之间的狭窄间隙内产生，而宽间隙保留介电材料。 在宽间隙内的电介质材料的保持能够形成理想的平面顶表面。 使用硬掩模层和选择性干蚀刻工艺使得能够在形成气隙之前避免湿加工步骤。 与典型的低k介电材料相比，气隙可以具有接近一个的介电常数，有利地减少互连电容。

    Methods for etching an etching stop layer utilizing a cyclical etching process
    157.
    发明授权
    Methods for etching an etching stop layer utilizing a cyclical etching process 有权
    利用循环蚀刻工艺蚀刻蚀刻停止层的方法

    公开(公告)号：US08980758B1

    公开(公告)日：2015-03-17

    申请号：US14029769

    申请日：2013-09-17

    Applicant: Applied Materials, Inc.

    Inventor： Mang-Mang Ling ,  Sean S. Kang ,  Jeremiah T. P. Pender ,  Srinivas D. Nemani ,  Bradley Howard

    IPC: H01L21/302 ,  H01L21/461 ,  H01L21/306

    CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J2237/334 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829

    Abstract: Methods for etching an etching stop layer disposed on the substrate using a cyclical etching process are provided. In one embodiment, a method for etching an etching stop layer includes performing a treatment process on the substrate having a silicon nitride layer disposed thereon by supplying a treatment gas mixture into the processing chamber to treat the silicon nitride layer, and performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process etches the treated silicon nitride layer.

    Abstract translation: 提供了使用循环蚀刻工艺蚀刻设置在基板上的蚀刻停止层的方法。 在一个实施例中，蚀刻停止层的蚀刻方法包括：通过将处理气体混合物供给到处理室中来对其上设置有氮化硅层的基板进行处理处理，以处理氮化硅层，并进行化学蚀刻工艺 在所述基板上通过向所述处理室供给化学蚀刻气体混合物，其中所述化学蚀刻气体混合物至少包含铵气体和三氟化氮，其中所述化学蚀刻工艺蚀刻所处理的氮化硅层。

    NEAR SURFACE ETCH SELECTIVITY ENHANCEMENT
    158.
    发明申请
    NEAR SURFACE ETCH SELECTIVITY ENHANCEMENT 审中-公开
    近表面蚀刻选择性增强

    公开(公告)号：US20140342569A1

    公开(公告)日：2014-11-20

    申请号：US13970481

    申请日：2013-08-19

    Applicant: Applied Materials, Inc.

    Inventor： Lina Zhu ,  Sean S. Kang ,  Srinivas D. Nemani ,  Sergey G. Belostotskiy ,  Jeremiah T. Pender

    IPC: H01L21/3065

    CPC classification number: H01L21/3065 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/32137

    Abstract: A method of selectively dry etching exposed substrate material on patterned heterogeneous structures is described. The method includes a plasma process prior to a remote plasma etch. The plasma process may use a biased plasma to treat an untreated substrate portion in a preferred direction to form a treated substrate portion. Subsequently, a remote plasma is formed using a fluorine-containing precursor to etch the treated substrate portion using the plasma effluents. By implementing biased plasma processes, the normally isotropic etch may be transformed into a directional (anisotropic) etch despite the remote nature of the plasma excitation during the etch process.

    Abstract translation: 描述了在图案化的异质结构上选择性地干蚀刻曝光的衬底材料的方法。 该方法包括在远程等离子体蚀刻之前的等离子体处理。 等离子体处理可以使用偏置的等离子体来处理优选方向上未处理的基板部分以形成经处理的基板部分。 随后，使用含氟前体形成远程等离子体，以使用等离子体流出物来蚀刻经处理的基底部分。 通过实施偏压等离子体处理，尽管在蚀刻过程中等离子体激发的远端性质，但是通常的各向同性蚀刻可以转化为定向（各向异性）蚀刻。

    DELICATE DRY CLEAN
    159.
    发明申请
    DELICATE DRY CLEAN 有权
    干燥干燥

    公开(公告)号：US20140342532A1

    公开(公告)日：2014-11-20

    申请号：US13966453

    申请日：2013-08-14

    Applicant: Applied Materials, Inc.

    Inventor： Lina Zhu ,  Sean S. Kang ,  Srinivas D. Nemani ,  Chia-Ling Kao

    IPC: H01L21/3105 ,  H01L21/311

    CPC classification number: H01L21/3105 ,  H01L21/02063 ,  H01L21/31116

    Abstract: A method of selectively removing fluorocarbon layers from overlying low-k dielectric material is described. These protective plasma treatments (PPT) are delicate alternatives to traditional post-etch treatments (PET). The method includes sequential exposure to (1) a local plasma formed from a silicon-fluorine precursor followed by (2) an exposure to plasma effluents formed in a remote plasma from a fluorine-containing precursor. The remote plasma etch (2) has been found to be highly selective of the residual material following the local plasma silicon-fluorine exposure. The sequential process (1)-(2) avoids exposing the low-k dielectric material to oxygen which would undesirably increase its dielectric constant.

    Abstract translation: 描述了从覆盖低k电介质材料中选择性除去碳氟化合物层的方法。 这些保护等离子体处理（PPT）是传统的蚀刻后处理（PET）的精巧替代品。 该方法包括连续暴露于（1）由硅 - 氟前体形成的局部等离子体，随后（2）暴露于在含氟前体的远程等离子体中形成的等离子体流出物。 已经发现远程等离子体蚀刻（2）对于局部等离子体硅 - 氟暴露后的残余材料是高度选择性的。 顺序方法（1） - （2）避免了将低k电介质材料暴露于氧气，这将不利地增加其介电常数。

    PATTERNING MAGNETIC MEMORY
    160.
    发明申请
    PATTERNING MAGNETIC MEMORY 审中-公开
    绘制磁记忆

    公开(公告)号：US20140308758A1

    公开(公告)日：2014-10-16

    申请号：US13934017

    申请日：2013-07-02

    Applicant: Applied Materials, Inc.

    Inventor： Srinivas D. Nemani ,  Sumit Agarwal ,  Jeremiah T. Pender ,  Jonathan Germain ,  Khoi Doan ,  Bradley Howard

    IPC: H01L43/12

    CPC classification number: H01L43/12

    Abstract: Methods of forming material junctions for magnetic memory devices are described. The methods involve providing a material stack including a bottom magnetic tunneling junction layer, a tunneling barrier layer, and a top magnetic tunneling junction layer (from bottom to top) on a substrate. The top magnetic tunneling junction layer is patterned to form a top magnetic tunneling junction and then a dielectric spacer layer may be formed over the top magnetic tunneling junction. The dielectric spacer is etched to leave a vertical dielectric spacer to maintain electrical separation between the top magnetic tunneling junction and the bottom magnetic tunneling junction during and following subsequent etching/processing. In an alternative embodiment the spacer layer is lithographically defined.

    Abstract translation: 描述了形成用于磁存储器件的材料结的方法。 所述方法包括在衬底上提供包括底部磁隧道结层，隧道势垒层和顶部磁性隧道结层（从底部到顶部）的材料堆叠。 将顶部磁隧道结层图案化以形成顶部磁性隧道结，然后可以在顶部磁性隧道结上方形成电介质间隔层。 蚀刻电介质间隔物以留下垂直电介质间隔物，以在随后的蚀刻/处理期间和之后保持顶部磁隧道结与底部磁性隧道结之间的电分离。 在替代实施例中，间隔层被光刻地限定。

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