公开(公告)号：US20160293775A1

公开(公告)日：2016-10-06

申请号：US15181621

申请日：2016-06-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Jun KOYAMA

IPC: H01L29/786 ,  G06K19/077 ,  H01L23/66

CPC classification number: H01L29/78696 ,  G06K19/07749 ,  G06K19/07773 ,  H01L23/66 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/7869 ,  H01L2223/6677 ,  H04B1/40 ,  Y02D70/00

Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.

公开(公告)号：US20160226471A1

公开(公告)日：2016-08-04

申请号：US15098391

申请日：2016-04-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Jun KOYAMA

IPC: H03K3/356 ,  H01L27/105 ,  H03K3/037

CPC classification number: H03K3/356104 ,  G11C7/04 ,  G11C14/0063 ,  G11C16/045 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/28202 ,  H01L21/28211 ,  H01L27/105 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/6659 ,  H03K3/0375 ,  H03K3/286 ,  H03K3/356 ,  H03K3/356121 ,  H03K3/356173

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.

公开(公告)号：US20160225325A1

公开(公告)日：2016-08-04

申请号：US15095528

申请日：2016-04-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA

IPC: G09G3/34

CPC classification number: G09G3/3406 ,  G09G3/3648 ,  G09G2300/0842 ,  G09G2320/0214 ,  G09G2320/0233 ,  G09G2320/04 ,  G09G2320/041 ,  G09G2320/10 ,  G09G2330/021 ,  G09G2330/023 ,  G09G2340/0435

Abstract: It is an object to provide a transmissive liquid crystal display device in which power consumption is reduced and deterioration in display quality is suppressed. As a backlight, a surface-emission light source is employed. The light source is a light source which performs surface light emission, so that the light emission area is large. Accordingly, the backlight can effectively radiate heat. Thus, even in the case where an image signal is not input to a pixel for a long period, the pixel can hold the image signal. In other words, both a reduction in power consumption and a suppression of deterioration in display quality can be realized.

Abstract translation: 本发明的目的是提供一种降低功耗并抑制显示质量劣化的透射式液晶显示装置。 作为背光，采用表面发射光源。 光源是进行表面发光的光源，因此发光面积大。 因此，背光源可以有效地散热。 因此，即使在图像信号未长时间输入到像素的情况下，像素也可以保持图像信号。 换句话说，可以实现功耗的降低和显示质量的劣化的抑制。

公开(公告)号：US20160155760A1

公开(公告)日：2016-06-02

申请号：US15019020

申请日：2016-02-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L27/115

CPC classification number: H01L27/1225 ,  G11C16/0416 ,  H01L27/1156

Abstract: An object is at least one of a longer data retention period of a memory circuit, a reduction in power consumption, a smaller circuit area, and an increase in the number of times written data can be read to one data writing operation. The memory circuit has a first field-effect transistor, a second field-effect transistor, and a rectifier element including a pair of current terminals. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of the pair of current terminals of the rectifier element is electrically connected to a source or a drain of the second field-effect transistor.

Abstract translation: 目的是存储电路的较长的数据保持期间，功耗的降低，较小的电路面积以及写入的数据的次数的增加可以读取到一个数据写入操作中的至少一个。 存储电路具有第一场效应晶体管，第二场效应晶体管和包括一对电流端子的整流元件。 数据信号被输入到第一场效应晶体管的源极和漏极之一。 第二场效应晶体管的栅极电连接到第一场效应晶体管的源极和漏极中的另一个。 整流元件的一对电流端子之一与第二场效应晶体管的源极或漏极电连接。

公开(公告)号：US20160079245A1

公开(公告)日：2016-03-17

申请号：US14950624

申请日：2015-11-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Keitaro IMAI ,  Jun KOYAMA

IPC: H01L27/108 ,  H01L29/786

CPC classification number: H01L27/10802 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/7869

Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10−13 A or less.

Abstract translation: 半导体器件包括：具有氧化物半导体层的晶体管; 以及使用除了氧化物半导体之外的半导体材料形成的逻辑电路。 晶体管的源电极和漏电极中的一个电连接到逻辑电路的至少一个输入端，并且至少一个输入信号通过晶体管施加到逻辑电路。 晶体管的截止电流优选为1×10-13A以下。

公开(公告)号：US20160043110A1

公开(公告)日：2016-02-11

申请号：US14817709

申请日：2015-08-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Masayuki SAKAKURA ,  Yoshitaka YAMAMOTO ,  Jun KOYAMA ,  Tetsuhiro TANAKA ,  Kazuki TANEMURA

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L29/78648

Abstract: A highly reliable semiconductor device that is suitable for high-speed operation is provided. A semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit has an arithmetic processing function. The second circuit includes a memory circuit. The memory circuit includes a transistor which includes a first conductor, a second conductor, a first insulator, a second insulator, and a semiconductor. The first conductor includes a region overlapping the semiconductor with the first insulator positioned between the first conductor and the semiconductor. The second conductor includes a region overlapping the semiconductor with the second insulator positioned between the second conductor and the semiconductor. The first conductor is capable of selecting on or off of the transistor. The third circuit is electrically connected to the second conductor, and is capable of changing the potential of the second conductor in synchronization with an operation of the transistor.

Abstract translation: 提供了一种适用于高速运行的高度可靠的半导体器件。 半导体器件包括第一电路，第二电路和第三电路。 第一电路具有算术处理功能。 第二电路包括存储电路。 存储电路包括晶体管，其包括第一导体，第二导​​体，第一绝缘体，第二绝缘体和半导体。 第一导体包括与半导体重叠的区域和位于第一导体和半导体之间的第一绝缘体。 第二导体包括与半导体重叠的区域，位于第二导体和半导体之间的第二绝缘体。 第一导体能够选择晶体管的导通或截止。 第三电路电连接到第二导体，并且能够与晶体管的操作同步地改变第二导体的电位。

公开(公告)号：US20150333090A1

公开(公告)日：2015-11-19

申请号：US14809767

申请日：2015-07-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE

IPC: H01L27/12 ,  H01L29/04 ,  H01L27/088 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L21/02603 ,  H01L27/0883 ,  H01L27/1251 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/045 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

Abstract translation: 晶体管使用本征或基本上固有的并且包括氧化物半导体层的表面部分中的结晶区域的氧化物半导体层。 使用从氧化物半导体去除作为电子给体（供体）的杂质并且具有比硅半导体更大的能隙的本征或本质上的本征半导体。 可以通过控制一对导电膜的电位来控制晶体管的电特性，所述一对导电膜相对于氧化物半导体层彼此相对设置，每个具有布置在其间的绝缘膜，使得沟道的位置 确定在氧化物半导体层中形成的氧化物半导体层。

公开(公告)号：US20150325595A1

公开(公告)日：2015-11-12

申请号：US14803358

申请日：2015-07-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kaoru HATANO

IPC: H01L27/12

CPC classification number: H01L27/127 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/41733

Abstract: It is an object of one embodiment of the present invention to manufacture a light-emitting display device by simplifying a manufacturing process of a transistor, without an increase in the number of steps as well as the number of photomasks as compared to those in the conventional case. A step for processing a semiconductor layer into an island shape is omitted by using a high-resistance oxide semiconductor which is intrinsic or substantially intrinsic for the semiconductor layer, used to form transistors. Formation of an opening in the semiconductor layer or an insulating layer formed over the semiconductor layer and etching of an unnecessary portion of the semiconductor layer are performed at the same time; thus, the number of photolithography steps is reduced.

Abstract translation: 本发明的一个实施方案的目的是通过简化晶体管的制造工艺来制造发光显示装置，而不增加步骤数量以及光掩模的数量，与常规的相比 案件。 通过使用用于形成晶体管的半导体层的固有或本质上的高电阻氧化物半导体来省略将半导体层加工成岛状的步骤。 在半导体层上形成开口或在半导体层上形成的绝缘层和对半导体层的不需要部分进行蚀刻的同时进行; 因此，光刻步骤的数量减少。

公开(公告)号：US20150255613A1

公开(公告)日：2015-09-10

申请号：US14662440

申请日：2015-03-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  G02F2001/136231 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/78606

Abstract: The display device includes a gate electrode, a gate insulating film provided over the gate electrode, a semiconductor film provided over the gate insulating film to overlap with the gate electrode, an island-shaped first insulating film provided over the semiconductor film to overlap with the gate electrode, a first conductive film provided over the semiconductor film, a pair of second conductive films which is provided over the semiconductor film and between which the first insulating film is sandwiched, and a second insulating film provided over the first insulating film, the first conductive film, and the pair of second conductive films. In the second insulating film and the semiconductor film, an opening portion which is positioned between the first conductive film and the one or the other of the pair of second conductive films is provided.

Abstract translation: 显示装置包括栅电极，设置在栅电极上的栅绝缘膜，设置在栅极绝缘膜上以与栅电极重叠的半导体膜，设置在半导体膜上方的岛状第一绝缘膜， 栅极电极，设置在半导体膜上的第一导电膜，设置在半导体膜上并且夹在第一绝缘膜之间的一对第二导电膜和设置在第一绝缘膜上的第二绝缘膜，第一绝缘膜 导电膜和一对第二导电膜。 在第二绝缘膜和半导体膜中，设置有位于第一导电膜与一对第二导电膜中的一个或另一个之间的开口部。

公开(公告)号：US20150243332A1

公开(公告)日：2015-08-27

申请号：US14625786

申请日：2015-02-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA

IPC: G11C5/06 ,  G11C11/418 ,  G11C5/10

CPC classification number: G11C5/063 ,  G11C5/10 ,  G11C8/16 ,  G11C11/40 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4096 ,  G11C11/418

Abstract: A semiconductor device with a small cell area and excellent data read/write capability is achieved. In the semiconductor device, a wiring for writing data is provided, and a first transistor with a low off-state current is turned on to supply data to a gate of a second transistor and is turned off so that electric charge corresponding to data is retained. Moreover, a wiring for reading data is provided, and a third transistor is turned on so that data is read out in accordance with the on/off state of the second transistor retaining the electric charge. With this configuration, data write and data read are achieved in the same cycle.

Abstract translation: 实现了具有小单元面积和优异的数据读/写能力的半导体器件。 在半导体装置中，设置用于写入数据的布线，并且导通具有低截止电流的第一晶体管，以将数据提供给第二晶体管的栅极，并将其关闭，使得与数据相对应的电荷被保留 。 此外，提供用于读取数据的布线，并且第三晶体管导通，使得根据保持电荷的第二晶体管的导通/截止状态读出数据。 通过这种配置，数据写入和数据读取可以在同一周期内实现。