公开(公告)号：US06887523B2

公开(公告)日：2005-05-03

申请号：US10326347

申请日：2002-12-20

申请人： Wei-Wei Zhuang ,  Sheng Teng Hsu ,  Wei Pan

发明人： Wei-Wei Zhuang ,  Sheng Teng Hsu ,  Wei Pan

IPC分类号： H01L21/205 ,  C23C16/40 ,  H01L21/316 ,  H01L27/10 ,  H01L45/00

CPC分类号： G11C13/0007 ,  C23C16/40 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1616

摘要： An MOCVD process is provided for forming metal-containing films having the general formula M′xM″(1−x)MyOz, wherein M′ is a metal selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Y, Sc, Yb, Lu, and Gd; M″ is a metal selected from the group consisting of Mg, Ca, Sr, Ba, Pb, Zn, and Cd; M is a metal selected from the group consisting of Mn, Ce, V, Fe, Co, Nb, Ta, Cr, Mo, W, Zr, Hf and Ni; x has a value from 0 to 1; y has a value of 0, 1 or 2; and z has an integer value of 1 through 7. The MOCVD process uses precursors selected from alkoxide precursors, β-diketonate precursors, and metal carbonyl precursors in combination to produce metal-containing films, including resistive memory materials.

摘要翻译： 提供了一种用于形成具有通式M 1，X 2，M 1，M 2，M 1，M 2， 其中M'是选自La，Ce，Pr，Nd，Pm，Sm，Y，Sc，Yb，Lu和Gd中的金属; M“是选自Mg，Ca，Sr，Ba，Pb，Zn和Cd的金属; M是选自Mn，Ce，V，Fe，Co，Nb，Ta，Cr，Mo，W，Zr，Hf和Ni中的金属; x的值为0到1; y的值为0,1或2; 并且z具有1至7的整数值.MOCVD方法组合使用选自醇盐前体，β-二酮前体和金属羰基前体的前体，以产生包含电阻记忆材料的含金属膜。

公开(公告)号：US06858905B2

公开(公告)日：2005-02-22

申请号：US10713327

申请日：2003-11-13

申请人： Sheng Teng Hsu ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L27/115 ,  G11C11/00 ,  G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L43/08 ,  H01L21/20

CPC分类号： H01L27/24 ,  G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/77

摘要： Low cross talk resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises a bit formed using a perovskite material interposed at a cross point of an upper electrode and lower electrode. Each bit has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit, decrease the resistivity of the bit, or determine the resistivity of the bit. Memory circuits are provided to aid in the programming and read out of the bit region.

摘要翻译： 提供了低串扰电阻交叉点存储器件，以及制造和使用方法。 存储装置包括使用插入在上电极和下电极的交叉点处的钙钛矿材料形成的钻头。 每个位具有响应于施加一个或多个电压脉冲而可以在一定范围内的值改变的电阻率。 可以使用电压脉冲来增加比特的电阻率，降低比特的电阻率，或者确定比特的电阻率。 提供存储器电路以帮助编程和读出位区域。

公开(公告)号：US06825086B2

公开(公告)日：2004-11-30

申请号：US10345728

申请日：2003-01-17

申请人： Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L21336

CPC分类号： H01L21/823878 ,  H01L21/76224 ,  H01L21/823807

摘要： A strained-silicon (Si) channel CMOS device shallow trench isolation (STI) oxide region, and method for forming same have been provided. The method comprises: forming a Si substrate; forming a relaxed-SiGe layer overlying the Si substrate, or a SiGe on insulator (SGOI) substrate with a buried oxide (BOX) layer; forming a strained-Si layer overlying the relaxed-SiGe layer; forming a silicon oxide layer overlying the strained-Si layer; forming a silicon nitride layer overlying the silicon oxide layer; etching the silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer, forming a STI trench with trench corners and a trench surface; forming a sacrificial oxide liner on the STI trench surface; in response to forming the sacrificial oxide liner, rounding and reducing stress at the STI trench corners; removing the sacrificial oxide liner; and, filling the STI trench with silicon oxide.

摘要翻译： 已经提供了应变硅（Si）沟道CMOS器件浅沟槽隔离（STI）氧化物区域及其形成方法。 该方法包括：形成Si衬底; 形成覆盖在Si衬底上的弛豫SiGe层或者具有掩埋氧化物（BOX）层的绝缘体上硅锗（SGOI）衬底; 形成覆盖弛豫SiGe层的应变Si层; 形成覆盖在应变Si层上的氧化硅层; 形成覆盖所述氧化硅层的氮化硅层; 蚀刻氮化硅层，氧化硅层，应变Si层和弛豫SiGe层，形成具有沟槽角和沟槽表面的STI沟槽; 在STI沟槽表面上形成牺牲氧化物衬垫; 响应于形成牺牲氧化物衬垫，在STI沟槽角处减少应力; 去除牺牲氧化物衬垫; 并用氧化硅填充STI沟槽。

公开(公告)号：US06699764B1

公开(公告)日：2004-03-02

申请号：US10238146

申请日：2002-09-09

申请人： Douglas J. Tweet ,  Jer-shen Maa ,  Jong-Jan Lee ,  Sheng Teng Hsu

发明人： Douglas J. Tweet ,  Jer-shen Maa ,  Jong-Jan Lee ,  Sheng Teng Hsu

IPC分类号： H01L21336

CPC分类号： H01L21/263 ,  C30B1/023 ,  C30B1/04 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02694 ,  H01L29/1054 ,  H01L29/165 ,  Y10S438/933

摘要： A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; epitaxially growing a silicon cap on the Si1−XGeX layer; implanting hydrogen ions through the Si1−XGeX layer to a depth of between about 3 nm to 100 nm below the Si1−XGeX/Si interface; amorphizing the Si1−XGeX layer to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

摘要翻译： 在硅衬底上制造Si1-XGeX膜的方法包括制备硅衬底; 在硅衬底上外延沉积形成Si1-XGeX / Si界面的Si1-XGeX层; 在Si1-XGeX层上外延生长硅帽; 通过Si1-XGeX层将氢离子注入Si1-XGeX / Si界面以下约3nm至100nm之间的深度; 将Si1-XGeX层非晶化以形成无定形的梯度SiGe层; 并在约650℃至1100℃的温度下对该结构退火约十秒至六十分钟以使SiGe层重结晶。

公开(公告)号：US06537361B2

公开(公告)日：2003-03-25

申请号：US09822637

申请日：2001-03-30

申请人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L2122

CPC分类号： H01L21/02197 ,  C01G21/00 ,  C01P2002/86 ,  H01L21/02112 ,  H01L21/02175 ,  H01L21/02282 ,  H01L21/31604 ,  H01L21/31691

摘要： A method of synthesizing a PGO spin-coating precursor solution includes utilizing the starting materials of lead acetate trihydrate (Pb(OAc)2•3H2O) and germanium alkoxide (Ge(OR)4(R=C2H5 and CH(CH3)2)). The organic solvent is di(ethylene glycol) ethyl ether. The mixed solution of lead and di(ethylene glycol) ethyl ether is heated in an atmosphere of air at a temperature no greater than 185° C., and preferably no greater than 190° C. for a time period in a range of thirty minutes to four hours. During the heating step the color of the solution is monitored to determine when the reaction is complete and when decomposition of the desired product begins to take place. The solution is then added to germanium di(ethylene glycol) ethyl ether to make the PGO spin-coating solution. This second step also entails heating the solution to a temperature no greater than 190° C. for a time period in a range of 0.5 to 2.0 hours. The process results in a PGO precursor solution suitable for use in spin-coating.

公开(公告)号：US06495377B2

公开(公告)日：2002-12-17

申请号：US09783817

申请日：2001-02-13

申请人： Sheng Teng Hsu

发明人： Sheng Teng Hsu

IPC分类号： H01L218242

CPC分类号： H01L29/6684 ,  H01L21/28291 ,  H01L29/78391

摘要： A method of fabricating a ferroelectric memory transistor includes preparing a substrate, including isolating an active region; forming a gate region; depositing an electrode plug in the gate region; depositing an oxide side wall about the electrode plug; implanting ions to form a source region and a drain region; annealing the structure to diffuse the implanted ions; depositing an intermediate oxide layer over the structure; removing the electrode plug; depositing a bottom electrode in place of the electrode plug; depositing a ferroelectric layer over the bottom electrode; depositing a top electrode over the ferroelectric layer; depositing a protective layer; depositing a passivation oxide layer over the structure; and metallizing the structure.

摘要翻译： 一种制造铁电存储晶体管的方法，包括：制备衬底，包括隔离有源区; 形成栅极区域; 在栅极区域中沉积电极塞; 在电极塞周围沉积氧化物侧壁; 注入离子以形成源区和漏区; 对结构退火以扩散注入的离子; 在所述结构上沉积中间氧化物层; 去除电极塞; 沉积底部电极代替电极塞; 在底部电极上沉​​积铁电层; 在所述铁电层上沉积顶部电极; 沉积保护层; 在结构上沉积钝化氧化物层; 并且对结构进行金属化。

公开(公告)号：US06352899B1

公开(公告)日：2002-03-05

申请号：US09497626

申请日：2000-02-03

申请人： Keizo Sakiyama ,  Sheng Teng Hsu

发明人： Keizo Sakiyama ,  Sheng Teng Hsu

IPC分类号： H01L21336

CPC分类号： H01L29/66772 ,  H01L21/76895 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66575 ,  H01L29/78618 ,  H01L29/78654

摘要： A method is provided for forming silicided source/drain electrodes in active devices in which the electrodes have very thin junction regions. In the process, adjacent active areas are separated by isolation regions, typically by LOCOS isolation, trench isolation or SOI/SIMOX isolation. A contact material, preferably silicide, is deposited over the wafer and the underling structures, including gate and interconnect electrodes. The silicide is then planed away using CMP, or another suitable planing process, to a height approximate the height of the highest structure. The silicide is then electrically isolated from the electrodes, using an etch back process, or other suitable process, to lower the silicide to a height below the height of the gate or interconnect electrode. The wafer is then patterned and etched to remove unwanted silicide. The remaining silicide typically forms silicided source regions and silicided drain regions that extend over a portion of the adjacent isolation regions such that the silicided source/drain regions are larger than the underlying source/drain regions to provide a larger contact area.

摘要翻译： 提供了一种在有源器件中形成硅化源极/漏极的方法，其中电极具有非常薄的结区域。 在该过程中，相邻的有源区域通过隔离区域分开，通常通过LOCOS隔离，沟槽隔离或SOI / SIMOX隔离。 接触材料，优选硅化物，沉积在晶片和底层结构上，包括栅极和互连电极。 然后使用CMP或另一种合适的刨削工艺将硅化物刨平到接近最高结构高度的高度。 然后使用回蚀工艺或其他合适的工艺将硅化物与电极电隔离，以将硅化物降低到低于栅极或互连电极的高度的高度。 然后将晶片图案化并蚀刻以除去不需要的硅化物。 剩余的硅化物通常形成在相邻隔离区域的一部分上延伸的硅化源区域和硅化物漏极区域，使得硅化源极/漏极区域大于下面的源极/漏极区域以提供更大的接触面积。

公开(公告)号：US06281589B1

公开(公告)日：2001-08-28

申请号：US09270901

申请日：1999-03-15

申请人： Tue Nguyen ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

发明人： Tue Nguyen ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21302

CPC分类号： C23G5/00 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/31111 ,  H01L21/31138 ,  H01L21/32134 ,  H01L21/76838

摘要： A system and method of selectively etching copper surfaces free of copper oxides in preparation for the deposition of an interconnecting metallic material is provided. The method removes metal oxides with &bgr;-diketones, such as Hhfac. The Hhfac is delivered into the system in vapor form, and reacts almost exclusively to copper oxides. The by-products of the cleaning process are likewise volatile for removal from the system with a vacuum pressure. Since the process is easily adaptable to most IC process systems, it can be conducted in an oxygen-free environment, without the removal of the IC from the process chamber. The in-situ cleaning process permits a minimum amount of copper oxide to reform before the deposition of the overlying interconnection metal. In this manner, a highly conductive electrical interconnection between the copper surface and the interconnecting metal material is formed. An IC having a metal interconnection, in which the underlying copper layer is cleaned of copper oxides, in-situ with Hhfac vapor, is also provided.

摘要翻译： 提供了一种选择性地蚀刻不含铜氧化物的铜表面以准备沉积互连金属材料的系统和方法。 该方法用β-二酮除去金属氧化物，如Hhfac。 Hhfac以蒸气形式输送到系统中，几乎完全与铜氧化物反应。 清洁过程的副产物同样是挥发性的，用于在真空压力下从系统中除去。 由于该方法很容易适用于大多数IC工艺系统，所以它可以在无氧环境中进行，而不会从处理室中移除IC。 在沉积互连金属之前，原位清洁工艺允许最小量的氧化铜重整。 以这种方式，形成铜表面和互连金属材料之间的高导电性电互连。 还提供了具有金属互连的IC，其中下面的铜层用Hhfac蒸气原位清除了铜氧化物。

公开(公告)号：US06242771B1

公开(公告)日：2001-06-05

申请号：US09291688

申请日：1999-04-13

申请人： Sheng Teng Hsu ,  Chien Hsiung Peng ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Chien Hsiung Peng ,  Jong Jan Lee

IPC分类号： H01L29788

CPC分类号： H01L28/55 ,  C23C16/40 ,  H01L21/31604 ,  H01L21/31691 ,  H01L29/516 ,  H01L29/78391

摘要： A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon includes: forming a silicon device area for the FEM gate unit; treating the device area to form area for a source, gate and drain region; depositing an FEM gate unit over the gate junction region, including depositing a lower electrode, depositing a c-axis oriented Pb5Ge3O11 FE layer by Chemical vapor deposition (CVD), and depositing an upper electrode; and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell includes: a single-crystal silicon substrate including an active region having source, gate and drain regions therein; a FEM gate unit including a lower electrode, a c-axis oriented Pb5Ge3O11 FE layer formed by CVD and an upper electrode; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and a source, gate and drain electrode.

摘要翻译： 在单晶硅的衬底上形成具有铁电存储（FEM）栅极单元的半导体结构的方法包括：形成用于FEM门单元的硅器件区域; 处理器件区域以形成源极，栅极和漏极区域; 在所述栅极结区域上沉积FEM栅极单元，包括沉积下电极，通过化学气相沉积（CVD）沉积c轴取向的Pb5Ge3O11FE层，以及沉积上电极; 以及围绕所述FEM门单元沉积绝缘结构。 铁电存储器（FEM）单元包括：单晶硅衬底，其包括其中具有源极，栅极和漏极区域的有源区; 包括下电极，由CVD形成的c轴取向Pb5Ge3O11FE层和上电极的有限元门单元; 绝缘层，具有覆盖接合区域的上表面，FEM门单元和衬底; 以及源极，栅极和漏极。

公开(公告)号：US6117691A

公开(公告)日：2000-09-12

申请号：US287726

申请日：1999-04-07

申请人： Sheng Teng Hsu ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Jong Jan Lee

IPC分类号： G11C11/22 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/115 ,  H01L29/78 ,  H01G7/06

CPC分类号： H01L21/84 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/11502 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/78391 ,  G11C11/223

摘要： A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate includes implanting doping impurities of a first type into the substrate to form a conductive channel of a first type, implanting doping impurities of a second type in the conductive channel of the first type to form a conductive channel well of a second type, implanting doping impurities of the first type in the conductive channel well of the second type to form a conductive channel of the first conductivity type for use as a gate junction region, implanting doping impurities of the second type in the conductive channel sub-well of the third type on either side of the gate junction region to form plural conductive channels of the second conductivity type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction region.A ferroelectric memory cell includes a silicon substrate of a first conductive type, a well structure of a second conductive type formed in the substrate, a structure of the first conductive type formed in the second conductivity type well structure, for use as a gate junction region. A source junction region and a drain junction region are located in the sub-well on either side of the gate junction region, doped to form conductive channels of second conductive type. A FEM gate unit overlays the conductive channel of the gate junction region. An insulating layer overlays the junction regions, the FEM gate unit and the substrate. Suitable electrodes are connected to the various active regions in the memory cell.

摘要翻译： 在硅衬底上形成具有铁电存储（FEM）栅极单元的半导体结构的方法包括将第一类型的掺杂杂质注入到衬底中以形成第一类型的导电沟道，将第二类型的掺杂杂质注入到 所述第一类型的导电通道形成第二类型的导电通道阱，在所述第二类型的导电通道阱中注入所述第一类型的掺杂杂质，以形成用作栅极结区域的第一导电类型的导电沟道 在栅极结区域的任一侧将第二类型的导电沟道子阱中的第二类型的掺杂杂质注入，以形成用作源极结区域和漏极结区域的第二导电类型的多个导电沟道; 以及在栅极结区域上沉积FEM栅极单元。 铁电存储单元包括第一导电类型的硅衬底，形成在衬底中的第二导电类型的阱结构，形成在第二导电类型阱结构中的第一导电类型的结构，用作栅极结区域 。 源极结区域和漏极结区域位于栅极结区域的任一侧的子阱中，被掺杂形成第二导电类型的导电沟道。 有限元栅极单元覆盖栅极结区域的导电沟道。 绝缘层覆盖了连接区域，FEM栅极单元和衬底。 合适的电极连接到存储单元中的各种有源区。