公开(公告)号：US20180166319A1

公开(公告)日：2018-06-14

申请号：US15376831

申请日：2016-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/7682 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

公开(公告)号：US20180122702A1

公开(公告)日：2018-05-03

申请号：US15846365

申请日：2017-12-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/49 ,  H01L27/088 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L21/82345 ,  H01L21/02181 ,  H01L21/28088 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A device includes a first transistor device having a first threshold voltage and including a first gate electrode structure positioned in a first gate cavity. The first gate electrode structure includes a first gate insulation layer, a first barrier layer, a first work function material layer formed above the first barrier layer, a second barrier layer formed above the first work function material layer, and a first conductive material formed above the second barrier layer. A second transistor device has a second threshold voltage different than the first threshold voltage and includes a second gate electrode structure positioned in a second cavity defined in the dielectric layer. The second gate electrode structure includes a second gate insulation layer, a second work function material layer, the second barrier layer formed above the second work function material layer, and a second conductive material formed above the second barrier layer.

公开(公告)号：US09947589B1

公开(公告)日：2018-04-17

申请号：US15600874

申请日：2017-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Lars W. Liebmann ,  Andre P. Labonte ,  Nigel G. Cave ,  Mark V. Raymond

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/535 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L21/823437 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76892 ,  H01L21/76895 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L23/535 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/785

Abstract: A transistor is formed above an active region. The transistor includes a gate structure, a first gate cap layer and a first sidewall spacer positioned adjacent sidewalls of the gate structure. Source/drain contacts are formed adjacent the first sidewall spacer. The first gate cap layer and a portion of the first sidewall spacer are removed to define a gate contact cavity that exposes a portion of the gate structure and an upper portion of the SD contacts. A second spacer and a conductive gate plug are formed in the gate contact cavity. Upper portions of the SD contacts positioned adjacent the second spacer are removed to define a gate cap cavity. A second gate cap layer is formed in the gate cap cavity. An insulating layer is formed above the second gate cap layer. A first conductive structure is formed in the insulating layer conductively coupled to the gate structure.

公开(公告)号：US20180096998A1

公开(公告)日：2018-04-05

申请号：US15689711

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Murat Kerem Akarvardar

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649

Abstract: Structures for the isolation of a fin-type field-effect transistor and methods of forming isolation for a fin-type field-effect transistor. A first dielectric layer is formed that encapsulates a plurality of fins. A second dielectric layer is formed that surrounds the first dielectric layer and the plurality of fins. A surface of the second dielectric layer relative to a surface of the first dielectric layer. A liner is conformally deposited on the surface of the first dielectric layer and on the recessed surface of the second dielectric layer. A section of the liner is removed to expose the surface of the first dielectric layer. The exposed surface of the first dielectric layer is recessed to reveal a portion of each of the plurality of fins.

公开(公告)号：US09929048B1

公开(公告)日：2018-03-27

申请号：US15388400

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre Labonte ,  Lars Liebmann

IPC: H01L21/768 ,  H01L21/033 ,  H01L29/66 ,  H01L23/535 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/535 ,  H01L29/66545

Abstract: Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.

公开(公告)号：US20170278844A1

公开(公告)日：2017-09-28

申请号：US15082242

申请日：2016-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC: H01L27/088 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US20170243790A1

公开(公告)日：2017-08-24

申请号：US15050540

申请日：2016-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Catherine B. Labelle ,  Chanro Park ,  Hoon Kim

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3105

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545

Abstract: A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is formed above the plurality of fins and the plurality of gate structures. The first mask layer has at least one fin cut opening and at least one gate cut opening defined therein. A first portion of a first fin of the plurality of fins disposed below the fin cut opening is removed to define a fin cut cavity. A second portion of a first gate structure of the plurality of gate structures disposed below the gate cut opening is removed to define a gate cut cavity. An insulating material layer is concurrently formed in at least a portion of the fin cut cavity and the gate cut cavity.

公开(公告)号：US20170179246A1

公开(公告)日：2017-06-22

申请号：US15451565

申请日：2017-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Xiuyu Cai

IPC: H01L29/423 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L21/311 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/4232 ,  H01L21/31144 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78

Abstract: One illustrative example of a transistor device disclosed herein includes, among other things, a gate structure, first and second spacers positioned adjacent opposite sides of the gate structure, and a multi-layer gate cap structure positioned above the gate structure and the upper surface of the spacers. The multi-layer gate cap structure includes a first gate cap material layer positioned on an upper surface of the gate structure and on the upper surfaces of the first and second spacers, a first high-k protection layer positioned on an upper surface of the first gate cap material layer and a second gate cap material layer positioned on an upper surface of the high-k protection layer. The first and second gate cap layers comprise different materials than the first high-k protection layer.

公开(公告)号：US09653356B2

公开(公告)日：2017-05-16

申请号：US14822340

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/768 ,  H01L21/02 ,  H01L27/088 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2221/1026 ,  H01L2221/1036

Abstract: One illustrative method disclosed includes, among other things, forming a silicon dioxide etch stop layer on and in contact with a source/drain region and adjacent silicon nitride sidewall spacers positioned on two laterally spaced-apart transistors having silicon dioxide gate cap layers, performing a first etching process through an opening in a layer of insulating material to remove the silicon nitride material positioned above the source/drain region, performing a second etching process to remove a portion of the silicon dioxide etch stop layer and thereby expose a portion of the source/drain region, and forming a conductive self-aligned contact that is conductively coupled to the source/drain region.

公开(公告)号：US09646884B2

公开(公告)日：2017-05-09

申请号：US14699122

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Sukwon Hong ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/28

CPC classification number: H01L21/823431 ,  H01L21/28088 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823481

Abstract: The present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a recess in the dielectric layer on each side of each fin, each recess being for a metal gate; forming sidewall spacers on each side of each recess; depositing a high-k dielectric liner in each recess and on a top surface of each of the fins; depositing a metal liner over the high-k dielectric layer; depositing a non-conformal organic layer (NCOL) over a top surface of the dielectric layer to pinch-off a top of each recess; depositing an OPL and ARC over the NCOL; etching the OPL, ARC and NCOL over a portion of the dielectric layer and recesses in a first region; and etching the portion of the recesses to remove residual NCOL present at a bottom of each recess of the portion of the recesses.