公开(公告)号：US10424482B2

公开(公告)日：2019-09-24

申请号：US15846779

申请日：2017-12-19

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li

IPC: H01L21/033 ,  H01L27/12 ,  H01L29/66 ,  H01L45/00 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of amorphous silicon germanium (a-SiGe) structures having a first percentage of germanium on a substrate, forming a plurality of spacers on sides of the plurality of a-SiGe structures, performing an annealing to convert a portion of each of the a-SiGe structures into respective portions comprising a-SiGe having a second percentage of germanium higher than the first percentage of germanium, and to convert each of the spacers into respective silicon oxide portions, removing from the substrate at least one of: one or more unconverted portions of the a-SiGe structures having the first percentage of germanium, one or more of the converted portions of a-SiGe structures, and one or more of the silicon oxide portions, and transferring a pattern to the substrate to form a plurality of patterned substrate portions, wherein the pattern includes the portions remaining after the removing.

公开(公告)号：US10418288B2

公开(公告)日：2019-09-17

申请号：US15863000

申请日：2018-01-05

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Shogo Mochizuki ,  Choonghyun Lee ,  Chun Wing Yeung

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/308 ,  H01L29/808 ,  H01L27/24 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28

Abstract: Techniques for forming VFETs having different gate lengths (and optionally different gate pitch and/or gate oxide thickness) on the same wafer are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a wafer including a first fin(s) patterned to a first depth and a second fin(s) patterned to a second depth, wherein the second depth is greater than the first depth; forming bottom source/drains at a base of the fins; forming bottom spacers on the bottom source/drains; forming gates alongside the fins, wherein the gates formed alongside the first fin(s) have a first gate length Lg1, wherein the gates formed alongside the second fin(s) have a second gate length Lg2, and wherein Lg1

公开(公告)号：US20190273026A1

公开(公告)日：2019-09-05

申请号：US15911838

申请日：2018-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Juntao Li ,  Peng Xu ,  Kangguo Cheng ,  Choonghyun Lee

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092

Abstract: A method for fabricating a semiconductor device having a uniform spacer thickness between field-effect transistors (FETs) associated with regions of the device is provided. A first semiconductor material is epitaxially grown in a first source/drain region within a first region of the device associated with a first FET. A capping layer is selectively formed on the first semiconductor material by forming a layer over the first and second regions that reacts with the first semiconductor material to form the capping layer. A second semiconductor material is epitaxially grown in a second source/drain region within a second region of the device associated with a second FET. The capping layer caps the growth of the first semiconductor material during the epitaxial growth of the second semiconductor material to provide the uniform spacer thickness between the first and second FETs.

公开(公告)号：US10395994B1

公开(公告)日：2019-08-27

申请号：US15911838

申请日：2018-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Juntao Li ,  Peng Xu ,  Kangguo Cheng ,  Choonghyun Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02

Abstract: A method for fabricating a semiconductor device having a uniform spacer thickness between field-effect transistors (FETs) associated with regions of the device is provided. A first semiconductor material is epitaxially grown in a first source/drain region within a first region of the device associated with a first FET. A capping layer is selectively formed on the first semiconductor material by forming a layer over the first and second regions that reacts with the first semiconductor material to form the capping layer. A second semiconductor material is epitaxially grown in a second source/drain region within a second region of the device associated with a second FET. The capping layer caps the growth of the first semiconductor material during the epitaxial growth of the second semiconductor material to provide the uniform spacer thickness between the first and second FETs.

公开(公告)号：US20190245049A1

公开(公告)日：2019-08-08

申请号：US15890671

申请日：2018-02-07

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Peng Xu

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L29/41791 ,  H01L21/324 ,  H01L21/76229 ,  H01L21/823431 ,  H01L29/6681 ,  H01L29/7851

Abstract: Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes laterally forming a spacer on a side of the semiconductor structure. The method further includes performing a thermal anneal on the semiconductor structure. The method further includes performing an etch to remove materials formed by the thermal anneal.

公开(公告)号：US20190214305A1

公开(公告)日：2019-07-11

申请号：US15863000

申请日：2018-01-05

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Shogo Mochizuki ,  Choonghyun Lee ,  Chun Wing Yeung

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/308

CPC classification number: H01L21/82385 ,  H01L21/28026 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0928 ,  H01L27/2454 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/8083

Abstract: Techniques for forming VFETs having different gate lengths (and optionally different gate pitch and/or gate oxide thickness) on the same wafer are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a wafer including a first fin(s) patterned to a first depth and a second fin(s) patterned to a second depth, wherein the second depth is greater than the first depth; forming bottom source/drains at a base of the fins; forming bottom spacers on the bottom source/drains; forming gates alongside the fins, wherein the gates formed alongside the first fin(s) have a first gate length Lg1, wherein the gates formed alongside the second fin(s) have a second gate length Lg2, and wherein Lg1

公开(公告)号：US10332999B1

公开(公告)日：2019-06-25

申请号：US15916525

申请日：2018-03-09

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Choonghyun Lee ,  Peng Xu ,  Heng Wu

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/08

Abstract: A method for manufacturing a semiconductor device includes patterning a strained semiconductor layer on a substrate into at least one strained fin, forming a plurality of dummy gates spaced apart from each other on the at least one strained fin, forming a spacer layer on the plurality of dummy gates, and on part of the at least one strained fin between the plurality of dummy gates, growing a plurality of source/drain regions on exposed portions of the at least one strained fin, removing the spacer layer from the part of the at least one strained fin between the plurality of dummy gates, and converting the part of the at least one strained fin between the plurality of dummy gates into at least one oxide.

公开(公告)号：US10332809B1

公开(公告)日：2019-06-25

申请号：US16014911

申请日：2018-06-21

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Jingyun Zhang ,  Choonghyun Lee ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L21/285 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor structure is provided that includes a pFET gate-all-around nanosheet structure and an nFET gate-all-around nanosheet structure integrated together on the same substrate. The pFET gate-all-around nanosheet structure contains a nickel monosilicide gate electrode layer that does not introduce strain into each suspended semiconductor channel material nanosheet of a first vertical stack of suspended semiconductor channel material nanosheets. The nFET gate-all-around nanosheet structure contains a Ni3Si gate electrode layer that introduces strain into each suspended semiconductor channel material nanosheet of a second vertical stack of suspended semiconductor channel material nanosheets.

公开(公告)号：US10325815B2

公开(公告)日：2019-06-18

申请号：US15963402

申请日：2018-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Choonghyun Lee ,  Shogo Mochizuki ,  Chun W. Yeung

IPC: H01L21/40 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.

公开(公告)号：US20190181236A1

公开(公告)日：2019-06-13

申请号：US15837321

申请日：2017-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Seyoung Kim ,  Injo Ok ,  Soon-Cheon Seo

IPC: H01L29/423 ,  H01L29/737 ,  H01L21/768 ,  H01L29/732 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66

Abstract: A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region.