公开(公告)号：US20230413586A1

公开(公告)日：2023-12-21

申请号：US18241954

申请日：2023-09-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H10B80/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H10B80/00 ,  H01L25/18 ,  H01L24/08 ,  H01L24/06 ,  H01L24/05 ,  H01L25/50 ,  H01L2224/05647 ,  H01L2224/05624 ,  H01L2224/08145 ,  H01L2224/06131 ,  H01L24/80 ,  H01L2224/80896

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors, the second level overlaying the first level; and at least four electronic circuit units (ECUs), where each of the ECUs include a first circuit, the first circuit including a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

公开(公告)号：US20230402098A1

公开(公告)日：2023-12-14

申请号：US18239117

申请日：2023-08-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: G11C16/04 ,  G11C11/408 ,  G11C16/08 ,  H10B80/00 ,  H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B12/00

CPC classification number: G11C16/0483 ,  G11C11/4087 ,  G11C16/08 ,  H10B80/00 ,  H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B12/30

Abstract: A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, and where the third level includes a plurality of decoder circuits.

公开(公告)号：US20230386890A1

公开(公告)日：2023-11-30

申请号：US18228907

申请日：2023-08-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/74

CPC classification number: H01L21/743

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors, including metal gate) atop the third metal layer; a fourth metal layer above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid including the fifth metal layer; a local power distribution grid, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer, a layer deposited by ALD.

公开(公告)号：US20230343632A1

公开(公告)日：2023-10-26

申请号：US18215062

申请日：2023-06-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC classification number: H01L21/6835 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B10/125 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B12/053 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L2924/13062 ,  H01L23/3677

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a raised source or raised drain transistor structure, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

公开(公告)号：US11793005B2

公开(公告)日：2023-10-17

申请号：US18105041

申请日：2023-02-02

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H10B63/00 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/78 ,  H01L29/423 ,  H10B10/00 ,  H10B12/00 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B61/00 ,  H01L27/105 ,  H10B41/40 ,  H10B43/40 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/84 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/7841 ,  H10B10/00 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B61/22 ,  H10B63/30 ,  H10B63/845 ,  H01L27/105 ,  H01L2029/7857 ,  H01L2221/6835 ,  H10B12/056 ,  H10B12/36 ,  H10B41/40 ,  H10B43/40 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8833

Abstract: A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said third single crystal channel is self-aligned to said fourth single crystal channel being processed following the same lithography step.

公开(公告)号：US11720736B2

公开(公告)日：2023-08-08

申请号：US18111567

申请日：2023-02-18

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F30/392 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/394

Abstract: A method of designing a 3D Integrated Circuit, the method including: partitioning at least one design into at least two levels, a first level and a second level; providing placement data of the second level; performing a placement of the first level using a placer executed by a computer, where the placement of the first level is based on the placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; and performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool.

公开(公告)号：US20230189538A1

公开(公告)日：2023-06-15

申请号：US18105856

申请日：2023-02-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H10B80/00

CPC classification number: H10B80/00

Abstract: A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; and a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells includes at least one second transistor, where the control circuits control access to the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least a portion of the array of memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.

公开(公告)号：US20230189537A1

公开(公告)日：2023-06-15

申请号：US18105041

申请日：2023-02-02

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H10B63/00 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/78 ,  H01L29/423 ,  H10B10/00 ,  H10B12/00 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B61/00

CPC classification number: H10B63/84 ,  H01L21/84 ,  H01L21/268 ,  H01L21/845 ,  H01L21/6835 ,  H01L21/8221 ,  H01L21/76254 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/785 ,  H01L29/7841 ,  H01L29/42392 ,  H10B10/00 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B61/22 ,  H10B63/30 ,  H10B63/845 ,  H01L27/105

Abstract: A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said third single crystal channel is self-aligned to said fourth single crystal channel being processed following the same lithography step.

公开(公告)号：US20230187414A1

公开(公告)日：2023-06-15

申请号：US18105826

申请日：2023-02-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L27/06 ,  H01L29/66 ,  H01L21/74 ,  H01L25/00 ,  H01L23/00 ,  H01L27/088

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L27/0688 ,  H01L29/66621 ,  H01L21/743 ,  H01L25/50 ,  H01L24/25 ,  H01L27/088 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/0002 ,  H01L27/092

Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the first level, where the fourth metal layer provides a global power distribution, and where a typical thickness of the fourth metal layer is at least 50% greater than a typical thickness of the third metal.

公开(公告)号：US20230170244A1

公开(公告)日：2023-06-01

申请号：US18092337

申请日：2023-01-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC classification number: H01L21/6835 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B10/125 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B12/053 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L2924/13062 ,  H01L23/3677

Abstract: A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said first transistors controls power delivery for at least one of said second transistor, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.